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GRACE-2: Integrating Fine-Grained Application Adaptations with Global Adaptation for Saving Energy Vibhore Vardhan, Daniel Sachs, Wanghong Yuan, Albert F. Harris III, Sarita Adve, Douglas Jones, Robin Kravets, and Klara Nahrstedt, To appear in the International Journal of Embedded Systems (IJES), Special Issue on "Low-Power Real-Time Embedded Computing". Invited paper. (Extended version of a paper in the Workshop on Power Aware Real-Time Computing (PARC), 2005.)
Statistical Fault Injection, Pradeep Ramachandran, Prabhakar Kudva, Jeffrey Kellington, John Schumann and Pia Sanda, to appear in the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
Trace-Based Microarchitecture-Level Diagnosis of Permanent Hardware Faults, Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, to appear in the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
Using Likely Program Invariants to Detect Hardware Errors, Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, to appear in the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
Online Estimation of Architectural Vulnerability Factor for Soft Errors, Xiaodong Li, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, to appear in the Proceedings of 35th International Symposium on Computer Architecture (ISCA '08), June 2008.
Foundations of the C++ Concurrency Memory Model, Hans-J. Boehm and Sarita V. Adve, to appear in the Proceedings of the Conference on Programming Language Design and Implementation (PLDI), June 2008.
Metrics for Architecture-Level Lifetime Reliability Analysis, Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers, and Jayanth Srinivasan to appear in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) April 2008.
SWAT: An Error Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , to appear in the Fourth Workshop on Silicon Errors in Logic - System Effects (SELSE - IV), March 2008.
OpenSPARC: An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar, Alan Wood, James C. Hoe, Babak Falsafi, Sarita V. Adve, Josep Torrellas, and Subhasish Mitra, to appear in the Fourth Workshop on Silicon Errors in Logic - System Effects (SELSE - IV), March 2008.
Understanding the Propagation of Hard Errors to Software and Implications for Resilient System Design, Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008 .
Joint Processor-Memory Adaptation for Energy , X. Li, R. Gupta, S. V. Adve, and Y. Zhou, in ACM Transactions on Architecture and Code Optimization (ACM TACO), vol. 4, no. 3, September 2007.
Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions , X. Li, S. V. Adve, P. Bose, and J. A. Rivers, To appear in the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2007. An extended version appears as Technical Report UIUCDCS-R-2007-2833, Department of Computer Science, University of Illinois, March 2007.
Towards a Hardware-Software Co-designed Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve and Yuanyuan Zhou , Third Workshop on Silicon Errors in Logic - System Effects (SELSE - III), April 2007.
ALP: Efficient Support for All Levels of Parallelism for Complex Media Applications, R. Sasanka, M. Li, S. V. Adve, Y.-K. Chen, E. Debes, ACM Transaction on Architecture and Code Optimization (ACM TACO), vol. 4, no. 1, article 3, March 2007.
Managing Energy-Performance Tradeoffs for Multithreaded Applications on Multiprocessor Architectures, Soyeon Park, Weihang Jiang, Yuanyuan Zhou, and Sarita Adve. To appear in the Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), 2007.
GRACE-1: Cross-Layer Adaptation for Multimedia Quality and Battery Energy, W. Yuan, K. Nahrstedt, S. V. Adve, R. H. Kravets, and D. L. Jones, IEEE Transactions on Mobile Computing, Vol.5, No. 7, July, 2006.
The ALPBench Benchmark Suite for Complex Multimedia Applications, Man-Lap Li, Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes. To appear in the Proceedings of the IEEE International Symposium on Workload Characterization (IISWC-2005), October 2005
Integrating Fine-Grained Application Adaptation with Global Adaptation for Saving Energy, V. Vardhan, D. G. Sachs, W. Yuan, A. F. Harris, S. V. Adve, D. L. Jones, R. H. Kravets, and K. Nahrstedt, Proceedings of the 2nd International Workshop on Power-Aware Real-Time Computing (PARC), September 2005.
Performance Directed Energy Management for Main Memory and Disks, X. Li, Z. Li, Y. Zhou, S. V. Adve, ACM Transactions on Storage, Vol 01, No. 03, August 2005. (Extended version of the paper in ASPLOS 2004.)
Lifetime Reliability: Toward an Architectural Solution, J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. IEEE Micro, special issue on Emerging Trends, vol. 25, issue 3, May-June 2005, 2-12.
The Importance of Heat-Sink Modeling for DTM and a Correction to "Predictive DTM for Multimedia Applications", Jayanth Srinivasan and Sarita V. Adve, To appear in the Proceedings of the Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) at ISCA-05, June 2005.
Exploiting Structural Duplication for Lifetime Reliability Enhancement, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA'05) June 2005. (Corrected version.)
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors, X. Li, S. V. Adve, P. Bose, and J. A. Rivers, To appear in the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2005.
SER Scaling Analysis of a Modern Superscalar Processor with SoftArch, X. Li, S. V. Adve, P. Bose, and J. A. Rivers, Proceedings of the 1^st Workshop on the System Effects of Logic Soft Errors (SELSE), April 2005.
Memory Side Prefetching for Linked Data Structures, C. J. Hughes and S. V. Adve. Journal of Parallel and Distributed Computing, February 2005, 448-463.
The Java Memory Model, Jeremy Manson, William Pugh, Sarita V. Adve, Proceedings of the 32nd Symposium on Principles of Programming Languages (POPL) Jan. 2005.
Performance-Directed Energy Management for Storage Systems, X. Li, Z. Li, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar. IEEE Micro, special issue on the Top Picks from Computer Architecture Conferences from October 2003 to October 2004, vol 24, issue 6, November-December 2004, 38-49. (One of thirteen papers chosen.)
Performance Directed Energy Management for Main Memory and Disks, Xiaodong Li, Zhengmin Li, Francis Davis, Pin Zhou, Yuanyuan Zhou, Sarita Adve, Sanjeev Kumar, Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '04) Oct. 2004.
A Reliability Odometer - Lemon Check Your Processor, J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, Wild and Crazy Ideas Session at the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), October 2004.
JSR 133: Java Memory Model and Thread Specification, July 2004. This is the product of the expert group for the Java Specification Request 133. The primary technical authors are: J. Manson, W. W. Pugh, and S. V. Adve.
The Impact of Technology Scaling on Lifetime Reliability, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, Proceedings of International Conference on Dependable Systems and Networks (DSN '04) June 2004.
The Energy Efficiency of CMP vs. SMT for Multimedia Workloads , R. Sasanka, S. V. Adve, Y. -K. Chen, and E. Debes, Proceedings of the 18th Annual ACM International Conference on Supercomputing (ICS '04) June 2004.
The Case for Lifetime Reliability-Aware Microprocessors, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, Proceedings of 31st International Symposium on Computer Architecture (ISCA '04) June 2004.
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications, Christopher J. Hughes and Sarita V. Adve, Proceedings of 31st International Symposium on Computer Architecture (ISCA '04) June 2004.
GRACE: A Hierarchical Adaptation Framework for Saving Energy, D.G. Sachs, W. Yuan, C.J. Hughes, A. Harris, S.V. Adve, D.L. Jones, R.H. Kravets, and K. Nahrstedt, Department of Computer Science, University of Illinois Technical Report UIUCDCS-R-2004-2409, February 2004.
GRACE: A Cross-Layer Adaptation Framework for Saving Energy, D. G. Sachs, W. Yuan, C. J. Hughes, A. F. Harris, S. V. Adve, D. L. Jones, R. H. Kravets, and K. Nahrstedt, Sidebar in IEEE Computer, special issue on Power-Aware Computing, December 2003, 50-51.
Adaptive Video Coding to Reduce Energy on Adaptive General-Purpose Processors, D. G. Sachs, S. Adve, D. L. Jones, Proceedings of the International Conference on Image Processing 2003 (ICIP '03), September 2003.
Predictive Dynamic Thermal Management for Multimedia Applications , Jayanth Srinivasan and Sarita V. Adve, Proceedings of the 17th Annual ACM International Conference on Supercomputing (ICS '03) June 2003, 109-120. See correction in WDDD'05.
Design and Evaluation of A Cross-Layer Adaptation Framework for Mobile Multimedia Systems, Wanghong Yuan, Klara Nahrstedt, Sarita V. Adve, Douglas L. Jones, and Robin H. Kravets, Proceedings of the SPIE Conference on Multimedia Computing and Networking, January 2003.
Soft Real-Time Scheduling on a Simultaneous Multithreaded Processor, R. Jain, C. J. Hughes, and S. V. Adve, Proceedings of the 23rd IEEE International Real-Time Systems Symposium (RTSS-2002), December 2002.
Joint Local and Global Hardware Adaptations for Energy, Ruchira Sasanka, Christopher J. Hughes, and Sarita V. Adve, To appear in the Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.
The Illinois GRACE Project: Global Resource Adaptation through CoopEration, Sarita V. Adve, Albert F. Harris, Christopher J. Hughes, Douglas L. Jones, Robin H. Kravets, Klara Nahrstedt, Daniel Grobe Sachs, Ruchira Sasanka, Jayanth Srinivasan, and Wanghong Yuan, Proceedings of the Workshop on Self-Healing, Adaptive, and self-MANaged Systems (SHAMAN) (held in conjunction with the 16th Annual ACM International Conference on Supercomputing), June 2002.
RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors, C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, IEEE Computer, vol. 35, no. 2, special issue on high performance simulators, February 2002, 40-49.
Performance Simulation Tools, S. S. Mukherjee, S. V. Adve, T. Austin, J. Emer, and P. S. Magnusson, IEEE Computer, vol. 29, no. 12, guest editors' introduction to the special issue on high performance simulators, February 2002, 38-39.
Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications, C. J. Hughes, J. Srinivasan, and S. V. Adve, Proceedings of the 34th International Symposium on Microarchitecture (MICRO-34), December 2001, 250-261. Click here for supplemental data.
Position Paper for NSF Workshop on Computer Performance Evaluation, S. V. Adve, December 2001.
Comparing and Combining Read Miss Clustering and Software Prefetching, V. S. Pai and S. V. Adve, Proceedings of the International Symposium on Parallel Architectures and Compilation Techniques, September 2001, 292-303.
Variability in the Execution of Multimedia Applications and Implications for Architecture, C. J. Hughes, P. Kaul, S. V. Adve, R. Jain, C. Park, and J. Srinivasan, Proceedings of the 28th International Symposium on Computer Architecture, June 2001, 254-265.
Reconfigurable Caches and their Application to Media Processing, P. Ranganathan, S. V.Adve, and N. P. Jouppi, Proceedings of the 27th International Symposium on Computer Architecture, June 2000, 214-224.
Code Transformations to Improve Memory Parallelism , V. S. Pai and S. V. Adve, The Journal of Instruction Level Parallelism, special issue on the best papers from MICRO-32, vol. 2, May 2000 (http://www.jilp.org/vol2). A shorter version of this paper appeared in the Proceedings of the 32nd International Symposium on Microarchitecture (MICRO-32), November 1999, 147-155.
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions , P. Ranganathan, S. V. Adve, and N. P. Jouppi, Proceedings of the 26th International Symposium on Computer Architecture, May 1999, 124-135.
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors, M. Durbhakula, V. S. Pai, and S. V. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, January 1999, 23-32. An extended version with some additional data appears as Technical Report #9802, Department of Electrical and Computer Engineering, Rice University, April 1998, revised December 1998.
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors , V. S. Pai, P. Ranganathan, H. Abdel-Shafi, and S. V. Adve, IEEE Transactions on Computers, special issue on caches, vol. 48, no. 2, February 1999, 218-226.
Recent Advances in Memory Consistency Models for Hardware Shared-Memory Systems, , S. V. Adve, V. S. Pai, and P. Ranganathan, Proceedings of the IEEE, special issue on distributed shared-memory, vol. 87, no. 3, March 1999, 445-455.
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors, P. Ranganathan, K. Gharachorloo, S. V. Adve, and L. A. Barroso, Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems,October 1998, 307-318.
Analytic Evaluation of Shared-Memory Systems with ILP Processors , D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, Proceedings of the 25th International Symposium on Computer Architecture, June 1998, 380-391.
A Customized MVA Model for ILP Multiprocessors , D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve, and D. A. Wood, Technical Report #1369, Computer Sciences Department, University of Wisconsin -- Madison, April 1998. Also available as Technical Report #9803, Department of Electrical and Computer Engineering, Rice University. (Provides details of the model discussed in the ISCA'98 paper above.)
Using Information From the Programmer to Implement System Optimizations Without Violating Sequential Consistency, S.V. Adve, Provisionally accepted for the Journal of Parallel and Distributed Computing (JPDC). Available as Rice University ECE Technical Report 9603, March 1996, revised June 1998.
A Retrospective on "Weak Ordering -- A New Definition", S. V. Adve and M. D. Hill, 25 Years of the International Symposia on Computer Architecture - Selected Papers (Gurindar S. Sohi, editor), ACM Press, 1998.
Changing Interaction of Compiler and Architecture , S.V. Adve, D.C. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith, C.H. Gebotys, M.T. Kandemir, D.J. Lilja, A.N. Choudhary, J.Z. Fang, and P.-C. Yew, IEEE Computer, 30 (12), December 1997, 51-58.
RSIM Reference Manual Version 1.0 , Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Technical Report 9705, Department of Electrical and Computer Engineering, Rice University, August 1997.
Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models , Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve, Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, June 1997, 199-210.
RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, IEEE Technical Committee on Computer Architecture newsletter, Fall 1997. An earlier version of this paper appeared in the Proceedings of the 3rd Workshop on Computer Architecture Education (held in conjunction with the 3rd International Symposium on High Performance Computer Architecture), February 1997.
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems, Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, and Sarita V. Adve, Proceedings of the 24th International Symposium on Computer Architecture, June 1997, 144-156.
An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors, Hazim Abdel-Shafi, Jonathan Hall, Sarita V. Adve, and Vikram S. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, February 1997, 204-215.
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodolgy, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Proceedings of the 3rd International Symposium on High Performance Computer Architecture, February 1997, 72-83.
Shared Memory Consistency Models: A Tutorial, S.V. Adve and K. Gharachorloo, IEEE Computer, December 1996, 66-76.
An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), October 1996, 12-23.
A Comparison of Entry Consistency and Lazy Release Consistency Implementations, S.V. Adve, A.L. Cox, S. Dwarkadas, R. Rajamony, and W. Zwaenepoel, Proceedings of the 2nd International Symposium on High Performance Computer Architecture, February 1996, 26-37.
Replacing Locks by Higher-Level Primitives, S.V. Adve, A.L. Cox, S. Dwarkadas, and W. Zwaenepoel, Technical Report #TR94-237, Department of Computer Science, Rice University, 1994. Presented at the Fourth Workshop on Scalable Shared-Memory Multiprocessors, Chicago, May 1994.
Designing Memory Consistency Models for Shared-Memory Multiprocessors, S. V. Adve, Ph.D. Thesis, Available as Computer Sciences Technical Report #1198, University of Wisconsin, Madison, December 1993.
Specifying System Requirements for Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Technical Report #CSL-TR-93-594, Stanford University, December 1993. Also available as Computer Sciences Technical Report #1199, University of Wisconsin, Madison, December 1993.
Sufficient System Requirements for Supporting the PLpc Memory Model, S.V. Adve, K. Gharachorloo, A. Gupta, J.L. Hennessy, and M.D. Hill, Computer Sciences Technical Report #1200, University of Wisconsin, Madison, December 1993. Also available as Technical Report #CSL-TR-93-595, Stanford University, December 1993.
A Unified Formalization of Four Shared-Memory Models, S.V. Adve and M.D. Hill, IEEE Transactions on Parallel and Distributed Systems 4, 6 (June 1993), 613-624.
Sufficient Conditions for Implementing the Data-Race-Free-1 Memory Model, S.V. Adve and M.D. Hill, Computer Sciences Technical Report #1107, University of Wisconsin, Madison, September 1992.
Programming for Different Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Journal of Parallel and Distributed Computing, August 1992, 399-407.
Comparison of Hardware and Software Cache Coherence Schemes, S.V. Adve, V.S. Adve, M.D. Hill, and M.K. Vernon, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 298-308. Also appears in The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions, edited by Milo Tomasevic and Veljko Milutinovic, IEEE Computer Society Press, 1993. An extended version appears in Computer Sciences Technical Report #1012, University of Wisconsin, Madison, March 1991.
Detecting Data Races on Weak Memory Systems, S.V. Adve, M.D. Hill, B.P. Miller, and R.H.B. Netzer, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 234-243.
Weak Ordering - A New Definition, S.V. Adve and M.D. Hill, Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990, 2-14.
Implementing Sequential Consistency in Cache-Based Systems, S.V. Adve and M.D. Hill, Proceedings of the 1990 International Conference on Parallel Processing, August 1990, I47-I50.

Ph.D. Theses

Lifetime Reliability Aware Microprocessors , Jayanth Srinivasan, 2006.
ALP: Energy Efficient Support for All Levels of Parallelism for Complex Media Applications, Ruchira Sasanka, 2005.
General-Purpose Processors for Multimedia Applications: Predictability and Energy Efficiency, Christopher Hughes, 2003.
Exploiting Instruction-Level Parallelism for Memory System Performance, Vijay Pai, 2000
General-Purpose Architectures for Media Processing and Database Workloads, Parthasarathy Ranganthan, 2000.

M.S. Theses

Limitations of the MTTF metric for architecture-level lifetime reliability analysis, Pradeep Ramachandran, 2007
Data-Level and Thread-Level Parallelism in Emerging Multimedia Applications, Man-Lap (Alex) Li, 2005
Integrated Global and Per-Application Cross-Layer Adaptations for Saving Energy, Vibhore Vardhan, 2004
Joint Processor-Memory Adaptation for Energy for General-Purpose Applications, Ritu Gupta, 2004
Architectural Adaptation for Thermal Control, Jayanth Srinivasan, 2002
Combining Intra-Frame with Inter-Frame Hardware Adaptations to Save Energy, Ruchira Sasanka, 2002
Soft Real-Time Scheduling on a Simultaneous Multithreaded Processor, Rohit Jain, 2002
Variability in the Execution of Multimedia Applications and Implications for Architecture, Praful Kaul, 2002
Prefetching Linked Data Structures in Sustems with Merged DRAM-Logic, Chris J. Hughes, 2002
Improving the Speed vs. Accuracy Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors, S. Murthy Durbhakula, 1998
Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors, Hazim Abdel-Shafi, 1997
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology, Vijay Pai, 1997
An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Parthasarathy Ranganathan, 1997