Group Publications

Papers

Talks

Ph.D. Theses

M.S. Theses

Papers

• SemanticXR: Low Power, Real-time Queryable Semantic Mapping with a Device-Cloud Architecture, Rahul Singh, Devdeep Ray, Connor Smith, Sarita Adve, in the IEEE Transactions on Visualization and Computer Graphics (TVCG). Also appears in the TVCG track of the Proceedings of the 25th IEEE International Symposium on Mixed and Augmented Reality (ISMAR), October 2026.
   
• Boba: Batched Simulation for Physics-Based Gaussian Digital Twins, Yihan Pang, Hanxiao Jiang, Sushant Kondguli, Sarita Adve, and Shenlong Wang, in the Proceedings of the European Conference on Computer Vision (ECCV), 2026.
   
• FlexGaussian: Flexible and Cost-Effective Training-Free Compression for 3D Gaussian Splatting, Boyuan Tian, Qizhe Gao, Siran Xianyu, Xiaotong Cui, Minjia Zhang, to appear in the 33rd ACM International Conference on Multimedia (MM), October 2025.
   
• Ada: A Distributed, Power-Aware, Real-Time Scene Provider for XR, Yihan Pang, Sushant Kondguli, Shenlong Wang, Sarita Adve, in the IEEE Transactions on Visualization and Computer Graphics (TVCG). Also appears in the TVCG track of the Proceedings of the 24th IEEE International Symposium on Mixed and Augmented Reality (ISMAR), October 2025. Best Paper Award.
   
• SRC Microelectronics & Advanced Packaging Technologies (MAPT) Roadmap, Version 2, Chapter 1, Section 1.3, Sarita Adve, Sonu Arora, Prashanth Hande, Qinjun Jiang, Mahesh Kallahalla, Sushant Kondguli, Michael Mahan, Yihan Pang, Anthony Rowe, Rob Shearer, Rahul Singh, Boyuan Tian, September 2025.
   
• EPOCHS-1: A 12nm Highly Heterogeneous Open-Source SoC with Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation, Joseph Zuckerman, Martin Cochet, Maico Cassel dos Santos, Erik Jens Loscalzo, Karthik Swaminathan, Tianyu Jia, Davide Giri, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Samira Zaliasl, Michael Lekas, Stephen Cahill, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, Sarita Adve, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Pradip Bose, Luca P. Carloni, in the IEEE Journal of Solid-State Circuits (JSSC), September 2025.
   
• XRgo: Design and Evaluation of Rendering Offload for Low-Power Extended Reality Devices, Steven Gao, Jeffrey Liu, Qinjun Jiang, William Sentosa, Brighten Godfrey, Sarita Adve, in the 16th ACM Multimedia System Conference (MMSys), March 2025.
   
• RemoteVIO: Offloading Head Tracking in an End-to-End XR System, Qinjun Jiang, Yihan Pang, William Sentosa, Steven Gao, Muhammad Huzaifa, Jeffrey Zhang, Javier Perez-Ramirez, Dibakar Das, David Gonzalez-Aguirre, Brighten Godfrey, Sarita Adve, in the 16th ACM Multimedia System Conference (MMSys), March 2025.
   
• FastFlip: Compositional SDC Resiliency Analysis, Keyur Joshi, Rahul Singh, Tommaso Bassetto, Sarita Adve, Darko Marinov, Sasa Misailovic, in the 2025 International Symposium on Code Generation and Optimization (CGO), March 2025.
   
• Is WTSN the missing piece for low latency in general-purpose Wi-Fi?, Milind Kumar Vaddiraju, William Sentosa, Qinjun Jiang, Sarita Adve, Dave Cavalcanti, Dibakar Das, Philip Brighten Godfrey, Javier Ramirez-Perez, Deepak Vasisht, in the 26th International Workshop on Mobile Computing Systems and Applications (HotMobile), February 2025.
   
• Transforming the Hybrid Cloud for Emerging AI Workloads, Deming Chen, Alaa Youssef, Ruchi Pendse, Andre Schleife, Bryan K. Clark, Hendrik Hamann, Jingrui He, Teodoro Laino, Lav Varshney, Yuxiong Wang, Avirup Sil, Reyhaneh Jabbarvand, Tianyin Xu, Volodymyr Kindratenko, Carlos Costa, Sarita Adve, Charith Mendis, Minjia Zhang, Santiago Nunez-Corrales, Raghu Ganti, Mudhakar Srivatsa, Nam Sung Kim, Josep Torrellas, Jian Huang, Seetharami Seelam, Klara Nahrstedt, Tarek Abdelzaher, Tamar Eilam, Huimin Zhao, Matteo Manica, Ravishankar Iyer, Martin Hirzel, Vikram Adve, Darko Marinov, Hubertus Franke, Hanghang Tong, Elizabeth Ainsworth, Han Zhao, Deepak Vasisht, Minh Do, Fabio Oliveira, Giovanni Pacifici, Ruchir Puri, Priya Nagpurkar, IBM-Illinois Discovery Accelerator Institute (IIDAI) White Paper, November 2024.
   
• Towards Energy-Efficiency by Navigating the Trilemma of Energy, Latency, and Accuracy, Boyuan Tian, Yihan Pang, Muhammad Huzaifa, Shenlong Wang, Sarita Adve, in the 23rd IEEE International Symposium on Mixed and Augmented Reality (ISMAR), October 2024.
   
• Mozart: Taming Taxes and Composing Accelerators with Shared-Memory, Vignesh Suresh, Bakshree Mishra, Ying Jing, Zeran Zhu, Naiyin Jin, Charles Block, Paolo Mantovani, Davide Giri, Joseph Zuckerman, Luca Carloni, Sarita Adve, in the 2024 International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2024.
   
• Under-canopy dataset for advancing simultaneous localization and mapping in agricultural robotics, Jose Cuaran, Andres Eduardo Baquero Velasquez, Mateus Valverde Gasparino, Naveen Kumar Uppalapati, Arun Narenthiran Sivakumar, Justin Wasserman, Muhammad Huzaifa, Sarita Adve, Girish Chowdhary, The International Journal of Robotics Research, May 2024.
   
• A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration, Maico Cassel Dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita Adve, Pradip Bose, David Brooks, Luca P Carloni, Kenneth L Shepard, Gu-Yeon Wei, in the 2024 IEEE International Solid-State Circuits Conference (ISSCC), February 2024.
   
• IMMERSE White Paper, November 2023.
   
• ApproxCaliper: A Programmable Framework for Application-aware Neural Network Optimization, Yifan Zhao, Hashim Sharif, Peter Pao-Huang, Vatsin Ninad Shah, Arun Narenthiran Sivakumar, Mateus Valverde Gasparino, Abdulrahman Mahmoud, Nathan Zhao, Sarita Adve, Girish Chowdhary, Sasa Misailovic, Vikram Adve, in the 6th Conference on Machine Learning and Systems (MLSys), June 2023.
   
• Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration, Georgios Zacharopoulos, Adel Ejjeh, Ying Jing, En-Yu Yang, Tianyu Jia, Iulian Brumar, Jeremy Intan, Muhammad Huzaifa, Sarita Adve, Vikram Adve, Gu-Yeon Wei, David Brooks, ACM Transactions on Embedded Computing Systems (TECS), May 2023.
   
• Power, Performance, and Image Quality Tradeoffs in Foveated Rendering, Rahul Singh, Muhammad Huzaifa, Jeffrey Liu, Anjul Patney, Hashim Sharif, Yifan Zhao, Sarita Adve, in the 30th IEEE Conference on Virtual Reality and 3D User Interfaces (IEEE VR), March 2023.
   
• FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity, Behzad Boroujerdian, Ying Jing, Devashree Tripathy, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi, ACM Transactions on Embedded Computing Systems (TECS), January 2023.
   
• Coordinated Science Laboratory 70th Anniversary Symposium: The Future of Computing, Klara Nahrstedt, Naresh Shanbhag, Vikram Adve, Nancy Amato, Romit Roy Choudhury, Carl Gunter, Nam Sung Kim, Olgica Milenkovic, Sayan Mitra, Lav Varshney, Yurii Vlasov, Sarita Adve, Rashid Bashir, Andreas Cangellaris, James DiCarlo, Katie Driggs-Campbell, Nick Feamster, Mattia Gazzola, Karrie Karahalios, Sanmi Koyejo, Paul Kwiat, Bo Li, Negar Mehr, Ravish Mehra, Andrew Miller, Daniela Rus, Alex Schwing, Anshumali Shrivastava, CoRR abs/2201.08974, October 2022.
   
• On-Device CPU Scheduling for Robot Systems, Aditi Partap, Samuel Grayson, Muhammad Huzaifa, Sarita Adve, Brighten Godfrey, Saurabh Gupta, Kris Hauser, Radhika Mittal, in the 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), October 2022. Extended version appears as arXiv:2207.13280v1 [cs.RO], July 2022.
   
• ILLIXR: An Open Testbed to Enable Extended Reality Systems Research, Muhammad Huzaifa, Rishi Desai, Samuel Grayson, Xutao Jiang, Ying Jing, Jae Lee, Fang Lu, Yihan Pang, Joseph Ravichandran, Finn Sinclair, Boyuan Tian,Hengzhi Yuan, Jeffrey Zhang, Sarita Adve, IEEE Micro, special issue on the Top Picks from the 2021 Computer Architecture Conferences, vol. 42, issue 4, July - August 2022. (One of the twelve papers chosen.)
   
• HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems, Adel Ejjeh, Aaron Councilman, Akash Kothari, Maria Kotsifakou, Leon Medvinsky, Abdul Rafae Noor, Hashim Sharif, Yifan Zhao, Sarita Adve, Sasa Misailovic, Vikram Adve, IEEE Micro Special Issue SI: Compiling for Accelerators, June 2022.
   
• A Case for Fine-grain Coherence Specialization in Heterogeneous Systems, Johnathan Alsop, Weon Taek Na, Matthew D. Sinclair, Samuel Grayson, Sarita V. Adve, ACM Transactions on Architecture and Code Optimization (TACO), April 2022.
   
• ILLIXR: Enabling End-to-End Extended Reality Research, Muhammad Huzaifa, Rishi Desai, Samuel Grayson, Xutao Jiang, Ying Jing, Jae Lee, Fang Lu, Yihan Pang, Joseph Ravichandran, Finn Sinclair, Boyuan Tian, Hengzhi Yuan, Jeffrey Zhang, Sarita V. Adve, in the 2021 IEEE International Symposium on Workload Characterization (IISWC), November 2021. Best Paper Award. Selected as an IEEE MICRO Top Picks from the 2021 Computer Architecture Conferences.
   
• Optimizing Selective Protection for CNN Resilience, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, and Stephen W. Keckler, in the 32nd International Symposium on Software Reliability Engineering (ISSRE), October 2021.
   
• ApproxTuner: A Compiler and Runtime System for Adaptive Approximations, Hashim Sharif, Yifan Zhao, Maria Kotsifakou, Akash Kothari, Ben Schreiber, Elizabeth Wang, Yasmin Sarita, Nathan Zhao, Keyur Joshi, Vikram S. Adve, Sasa Misailovic, Sarita Adve, in the Principles and Practice of Parallel Programming (PPoPP), February 2021.
   
• Inter-kernel Reuse-aware Thread Block Scheduling, Muhammad Huzaifa, Johnathan Alsop, Abdulrahman Mahmoud, Giordano, Salvador, Matthew D. Sinclair, Sarita V. Adve, ACM Transactions on Architecture and Code Optimization (TACO), August 2020.
   
• PyTorchFI: A Runtime Perturbation Tool for DNNs, Abdulrahman Mahmoud, Neeraj Aggarwal, Alex Nobbe, Jose Rodrigo Sanchez Vicarte, Sarita V. Adve, Christopher W. Fletcher, Iuri Frosio, Siva Kumar Sastry Hari, in the IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume 2020, presented at the Workshop on Dependable and Secure Machine Learning (DSML), June 2020.
   
• Specializing Coherence, Consistency, and Push/Pull for GPU Graph Analytics, Giordano Salvador, Johnathan Alsop, Wesley H. Darvin, Muhammad Huzaifa, Matthew D. Sinclair, Sarita V. Adve , as an extended abstract at 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020.
   
• Future Directions for Parallel and Distributed Computing, Scott D. Stoller, Michael Carbin, Sarita Adve, Kunal Agrawal, Guy Blelloch, Dan Stanzione, Katherine Yelick, and Matei Zaharia. Report of an NSF workshop to influence the successor to the Scalable Parallelism in the Extreme (SPX) program, October 2019.
   
• ApproxHPVM: A Portable Compiler IR for Accuracy-aware Optimizations, Hashim Sharif, Prakalp Srivastava, Muhammad Huzaifa, Maria Kotsifakou, Keyur Joshi, Yasmin Sarita, Nathan Zhou, Vikram Adve, Sasa Misailovic, and Sarita Adve, in the Proceedings of the International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), October 2019.
   
• Approximate Checkers, Abdulrahman Mahmoud, Paul Reckamp, Panqiu Tang, Christopher W. Fletcher, and Sarita V. Adve, in the 2019 Workshop on Approximate Computing Across the Stack (WAX), June 2019.
   
• gem5-Approxilyzer: An Open-Source Tool for Application-Level Soft Error Analysis , Radha Venkatagiri, Khalique Ahmed, Abdulrahman Mahmoud, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, Sarita V. Adve, in the 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2019.
   
• Minotaur: Adapting Software Testing Techniques for Hardware Errors, Abdulrahman Mahmoud, Radha Venkatagiri, Khalique Ahmed, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, Sarita V. Adve, in the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2019.
   
• Optimizing Software-Directed Instruction Replication for GPU Error Detection, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, and Stephen W. Keckler, in the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2018.
   
• Spandex: A Flexible Interface for Efficient Heterogeneous Coherence, Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve, in the 45th International Symposium on Computer Architecture (ISCA), June 2018.
   
• Impact of Software Approximations on the Resiliency of a Video Summarization System, Radha Venkatagiri, Karthik Swaminathan, Chung-Ching Lin, Liang Wang, Alper Buyuktosunoglu, Pradip Bose, and Sarita V. Adve, in the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2018.
   
• HPVM: Heterogeneous Parallel Virtual Machine, Maria Kotsifakou, Prakalp Srivastava, Matthew D. Sinclair, Rakesh Komuravelli, Vikram Adve, and Sarita Adve, in the Principles and Practice of Parallel Programming (PPoPP), February 2018.
   
• HeteroSync: A Benchmark Suite for Fine-Grained Synchronization on Tightly Coupled GPUs, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the IEEE International Symposium on Workload Characterization (IISWC), October 2017.
   
• Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the 44th International Symposium on Computer Architecture (ISCA), June 2017.
   
• Leveraging Software Testing to Explore Input Dependence for Approximate Computing, Abdulrahman Mahmoud, Radha Venkatagiri, Khalique Ahmed, Sarita V. Adve, Darko Marinov, and Sasa Misailovic in the 2017 Workshop on Approximate Computing Across the Stack (WAX), April 2017.
   
• Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Applications to Hardware Resiliency, Radha Venkatagiri, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, and Sarita V. Adve, in the 49th IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2016.
   
• Lazy Release Consistency for GPUs, Johnathan Alsop, Bradford Beckmann, Marc Orr, David Wood, in the 49th IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2016.
   
• Resilience Characterization of a Vision Analytics Application Under Varying Degrees of Approximation, Radha Venkatagiri, Karthik Swaminathan, Chung-Ching Lin, Liang Wang, Alper Buyuktosunoglu, Pradip Bose, and Sarita V. Adve, in the 2016 IEEE International Symposium on Workload Characterization (IISWC), September 2016.
   
• POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems, Prakalp Srivastava, Maria Kotsifakou, Matthew D. Sinclair, Rakesh Komuravelli, Vikram Adve, Sarita Adve, in the Proceedings of the 2016 International Conference on Parallel Architectures and Compilation (PACT), September 2016.
   
• Towards More Precision in Approximate Computing, Radha Venkatagiri, Abdulrahman Mahmoud, and Sarita V. Adve, in the 2016 Workshop on Approximate Computing Across the Stack (WAX), April 2016.
   
• GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs, Johnathan Alsop, Matthew D. Sinclair, Rakesh Komuravelli, and Sarita V. Adve, in the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
   
• Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)i, December 2015. Selected as an IEEE MICRO Top Picks Honorable Mention from the 2015 Computer Architecture Conferences
   
• Stash: Have Your Scratchpad and Cache it Too, Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram Adve, in the 42nd International Symposium on Computer Architecture (ISCA), June 2015. Selected as an IEEE MICRO Top Picks Honorable Mention from the 2015 Computer Architecture Conferences.
   
• DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations, Hyojin Sung, Sarita V. Adve, in the Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015 , March 2015.
   
• Eliminating On-Chip Traffic Waste: Are We There Yet?, Robert Smolinski, Rakesh Komuravelli, Hyojin Sung, and Sarita V. Adve, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015. Find an extended version of the paper here.
   
• Revisiting the Complexity of Hardware Cache Coherence and Some Implications, Rakesh Komuravelli, Sarita V. Adve, Ching-Tsun Chou, ACM Transactions on Architecture and Code Optimization (TACO), January 2015.
   
• Hardware Fault Recovery for I/O Intensive Applications, Pradeep Ramachandran, Siva Kumar Sastry Hari, Manlap Li, Sarita V. Adve, ACM Transactions on Architecture and Code Optimization (TACO), October 2014.
   
• GangES: Gang Error Simulation for Hardware Resiliency Evaluation, S. Hari, R. Venkatagiri, S. V. Adve, and H. Naeimi, in the Proceedings of the International Symposium on Computer Architecture (ISCA), June 2014.
   
• Addressing Failures in Exascale Computing, M. Snir, R. W. Wisniewski, J. A. Abraham, S. V. Adve, S. Bagchi, P. Balaji, J. Belak, P. Bose, F. Cappello, B. Carlson, A. A. Chien, P. Coteus, N. A. Debardeleben, P. Diniz, C. Engelmann, M. Erez, S. Fazzari, A. Geist, R. Gupta, F. Johnson, S. Krishnamoorthy, S. Leyffer, D. Liberty, S. Mitra, T. Munson, R. Schreiber, J. Stearley, E. V. Hensbergen. International Journal of High Performance Computing Applications, vol. 28, issue 2, May 2014, pp 129-173, first published online on March 21, 2014. (Preliminary version available as an ANL technical report.)
   
• DeNovoND: Efficient Hardware Support for Disciplined Non-determinism , Hyojin Sung, Rakesh Komuravelli, Sarita V. Adve, IEEE Micro, special issue on the Top Picks from the 2013 Computer Architecture Conferences, vol. 34, issue 3, May - June 2014. (One of twelve papers chosen.)
   
• ASPLOS'14 Program Chair's Message, Sarita V. Adve, in the Proceedings of 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014. Slides from the program chair's welcome and report at ASPLOS'14.
   
• Relyzer: Application Resiliency Analyzer for Transient Faults, S. Hari, S. V. Adve, H. Naeimi, and P. Ramachandran. In IEEE Micro, special issue on the Top Picks from the 2012 Computer Architecture Conferences, vol. 33, issue 3, May - June 2013. (One of eleven papers chosen.)
   
• DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism, Hyojin Sung, Rakesh Komuravelli, Sarita V. Adve, in the Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems (ASPLOS), March 2013.
   
• Virtual Instruction Set Computing for Heterogeneous Systems, Vikram Adve, Sarita Adve, Rakesh Komuravelli, Matthew D. Sinclair, and Prakalp Srivastava, 4th USENIX Workshop on Hot Topics in Parallelism (HotPar), June 2012.
   
• Low-cost Program-level Detectors for Reducing Silent Data Corruptions, Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2012.
   
• 21st Century Computer Architecture, A community white paper, Computing Community Consortium, May 2012. Chinese translation by State Key Laboratory of Computer Architecture (SKL-Carch) and republication: Computing Community Consortium (CCC), 21st Century Computer Architecture, Communication of the China Computer Federation (CCF), 2012, Volume 8, Issue 12, p70-81.
   
• CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions, A. Pellegrini, R. Smolinski, L. Chen, X. Fu, S. K. S. Hari, J. Jiang, S. V. Adve, T. Austin, V. Bertacco, in the Proceedings of the Design, Automation and Test in Europe (DATE) , March 2012.
   
• Relyzer: Exploiting Application-Level Fault Equivalence to Analyze Application Resiliency to Transient Faults, Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, and Pradeep Ramachandran, in the Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2012.
   
• Memory Models. S. V. Adve and H.-J. Boehm. In the Encyclopedia of Parallel Computing, Springer, 2012.
   
• You Don't Know Jack about Shared Variables or Memory Models. Communications of the ACM (CACM), vol. 55, no. 2, 2012. Also appears in ACM Queue vol. 9, no. 12, 2011.
   
• DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism, Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, and Ching-Tsun Chou, 20th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2011, Best Paper Award.
   
• Safe Nondeterminism in a Deterministic-by-Default Parallel Language, R. Bocchino, S. Heumann, N. Honarmand, S. Adve, V. Adve, A. Welc, and T. Shpeisman, 38th Symposium on Principles of Programming Languages (POPL), 2011.
   
• Understanding When Symptom Detectors Work by Studying Data-Only Application Values, Pradeep Ramachandran, Siva Kumar Sastry Hari, Sarita Adve, and Helia Naeimi, in the Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
   
• Relyzer: Application Resiliency Analyzer for Transient Faults, Siva Kumar Sastry Hari, Helia Naeimi, Pradeep Ramachandran, and Sarita Adve, in the Proceedings of IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
   
• Architectures for Online Error Detection and Recovery in Multicore Processors, Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel Sorin, Albert Meixner, Arijit Biswas, and Xavier Vera, Proceedings of the Design, Automation and Test in Europe (DATE), March 2011.
   
• Data Races are Evil with No Exceptions, S. V. Adve, in the Communications of the ACM (CACM), vol. 53, no. 11, 2010. A technical perspective on a research highlight.
   
• Parallel SAH k-D Tree Construction, Byn Choi, Rakesh Komuravelli, Victor Lu, Hyojin Sung, Robert L. Bocchino, Sarita V. Adve, and John C. Hart, High Performance Graphics (HPG), 2010.
   
• DeNovo: Rethinking Hardware for Disciplined Parallelism, Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Bocchino, Sarita V. Adve, and Vikram V. Adve, Second USENIX Workshop on Hot Topics in Parallelism (HotPar), 2010.
   
• A Language for Deterministic-by-Default Parallel Programming, Robert Bocchino, Vikram S. Adve, Danny Dig., Sarita V. Adve, Stephen Heumann, Rakesh Komuravelli, Jeffery Overbey, Patrick Simmons, Hyojin Sung, Mohsen Vakilian, and Marc Snir, 15th Workshop on Compilers for Parallel Computing (CPC 2010).
   
• Memory Models: A Case for Rethinking Parallel Languages and Hardware, S. V. Adve and H.-J. Boehm, in the Communications of the ACM (CACM). vol. 53, no. 8, 2010.
   
• Rethinking Hardware (and Software) for Disciplined Parallelism, Sarita V. Adve, position paper for the "Advancing Computer Architecture Research" workshop sponsored by CRA/CCC, February 2010.
   
• mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems, Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, and Sarita V. Adve, in the Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), December 2009.
   
• A Type and Effect System for Deterministic Parallel Java, Robert Bocchino, Vikram S. Adve, Danny Dig., Sarita V. Adve, Stephen Heumann, Rakesh Komuravelli, Jeffery Overbey, Patrick Simmons, Hyojin Sung, and Mohsen Vakilian, in the Proceedings of the International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), 2009.
   
• Parallel Programming Must Be Deterministic by Default, R. Bocchino, V. Adve, S. Adve, and M. Snir. First USENIX Workshop on Hot Topics in Parallelism (HotPar), March 2009.
   
• GRACE-2: Integrating Fine-Grained Application Adaptations with Global Adaptation for Saving Energy Vibhore Vardhan, Daniel Sachs, Wanghong Yuan, Albert F. Harris III, Sarita Adve, Douglas Jones, Robin Kravets, and Klara Nahrstedt, in the International Journal of Embedded Systems (IJES), Special Issue on "Low-Power Real-Time Embedded Computing", Vol. 4, No. 2, 2009. (Extended version of a paper in the Workshop on Power Aware Real-Time Computing (PARC), 2005.)
   
• Accurate Microarchitecture-Level Fault Modeling for Studying Hardware Faults, Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, and Sarita V. Adve, Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009.
   
• Parallel Computing Research at Illinois: The UPCRC Agenda, Sarita V. Adve, Vikram S. Adve, Gul Agha, Matthew I. Frank, Maria J. Garzaran, John C. Hart, Wen-mei W. Hwu, Ralph E. Johnson, Laxmikant V. Kale, Rakesh Kumar, Darko Marinov, Klara Nahrstedt, David Padua, Madhusudan Parthasarathy, Sanjay J. Patel, Grigore Rosu, Dan Roth, Marc Snir, Josep Torrellas, and Craig Zilles, http://www.upcrc.illinois.edu/whitepaper.php, November 2008.
   
• Statistical Fault Injection, Pradeep Ramachandran, Prabhakar Kudva, Jeffrey Kellington, John Schumann and Pia Sanda, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
   
• Trace-Based Microarchitecture-Level Diagnosis of Permanent Hardware Faults, Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
   
• Using Likely Program Invariants to Detect Hardware Errors, Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
   
• Online Estimation of Architectural Vulnerability Factor for Soft Errors, Xiaodong Li, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, in the Proceedings of 35th International Symposium on Computer Architecture (ISCA '08), June 2008.
   
• Foundations of the C++ Concurrency Memory Model, Hans-J. Boehm and Sarita V. Adve, Proceedings of the Conference on Programming Language Design and Implementation (PLDI), June 2008.
   
• Metrics for Architecture-Level Lifetime Reliability Analysis, Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers, and Jayanth Srinivasan, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) April 2008.
   
• SWAT: An Error Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , Fourth Workshop on Silicon Errors in Logic - System Effects (SELSE - IV), March 2008.
   
• OpenSPARC: An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar, Alan Wood, James C. Hoe, Babak Falsafi, Sarita V. Adve, Josep Torrellas, and Subhasish Mitra, Fourth Workshop on Silicon Errors in Logic - System Effects (SELSE - IV), March 2008.
   
• Understanding the Propagation of Hard Errors to Software and Implications for Resilient System Design, Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008 .
   
• Joint Processor-Memory Adaptation for Energy , X. Li, R. Gupta, S. V. Adve, and Y. Zhou, in ACM Transactions on Architecture and Code Optimization (ACM TACO), vol. 4, no. 3, September 2007.
   
• Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions , X. Li, S. V. Adve, P. Bose, and J. A. Rivers, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2007. An extended version appears as Technical Report UIUCDCS-R-2007-2833, Department of Computer Science, University of Illinois, March 2007.
   
• Towards a Hardware-Software Co-designed Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve and Yuanyuan Zhou , Third Workshop on Silicon Errors in Logic - System Effects (SELSE - III), April 2007.
   
• ALP: Efficient Support for All Levels of Parallelism for Complex Media Applications, R. Sasanka, M. Li, S. V. Adve, Y.-K. Chen, E. Debes, ACM Transaction on Architecture and Code Optimization (ACM TACO), vol. 4, no. 1, article 3, March 2007.
   
• Managing Energy-Performance Tradeoffs for Multithreaded Applications on Multiprocessor Architectures, Soyeon Park, Weihang Jiang, Yuanyuan Zhou, and Sarita Adve. Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), 2007.
   
• GRACE-1: Cross-Layer Adaptation for Multimedia Quality and Battery Energy, W. Yuan, K. Nahrstedt, S. V. Adve, R. H. Kravets, and D. L. Jones, IEEE Transactions on Mobile Computing, Vol.5, No. 7, July, 2006.
   
• The ALPBench Benchmark Suite for Complex Multimedia Applications, Man-Lap Li, Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes. Proceedings of the IEEE International Symposium on Workload Characterization (IISWC-2005), October 2005
   
• Integrating Fine-Grained Application Adaptation with Global Adaptation for Saving Energy, V. Vardhan, D. G. Sachs, W. Yuan, A. F. Harris, S. V. Adve, D. L. Jones, R. H. Kravets, and K. Nahrstedt, Proceedings of the 2nd International Workshop on Power-Aware Real-Time Computing (PARC), September 2005.
   
• Performance Directed Energy Management for Main Memory and Disks, X. Li, Z. Li, Y. Zhou, S. V. Adve, ACM Transactions on Storage, Vol 01, No. 03, August 2005.  (Extended version of the paper in ASPLOS 2004.)
   
• Lifetime Reliability: Toward an Architectural Solution, J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. IEEE Micro, special issue on Emerging Trends, vol. 25, issue 3, May-June 2005, 2-12.
   
• The Importance of Heat-Sink Modeling for DTM and a Correction to "Predictive DTM for Multimedia Applications", Jayanth Srinivasan and Sarita V. Adve, Proceedings of the Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) at ISCA-05, June 2005.
   
• Exploiting Structural Duplication for Lifetime Reliability Enhancement, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA'05) June 2005. (Corrected version.)
   
• SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors, X. Li, S. V. Adve, P. Bose, and J. A. Rivers, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2005.
   
• SER Scaling Analysis of a Modern Superscalar Processor with SoftArch, X. Li, S. V. Adve, P. Bose, and J. A. Rivers, Proceedings of the 1^st Workshop on the System Effects of Logic Soft Errors (SELSE), April 2005.
   
• Memory Side Prefetching for Linked Data Structures, C. J. Hughes and S. V. Adve. Journal of Parallel and Distributed Computing, February 2005, 448-463.
   
• The Java Memory Model, Jeremy Manson, William Pugh, Sarita V. Adve, Proceedings of the 32nd Symposium on Principles of Programming Languages (POPL) Jan. 2005.
   
• Performance-Directed Energy Management for Storage Systems, X. Li, Z. Li, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar.  IEEE Micro, special issue on the Top Picks from Computer Architecture Conferences from October 2003 to October 2004, vol 24, issue 6, November-December 2004, 38-49. (One of thirteen papers chosen.)
   
• Performance Directed Energy Management for Main Memory and Disks, Xiaodong Li, Zhengmin Li, Francis Davis, Pin Zhou, Yuanyuan Zhou, Sarita Adve, Sanjeev Kumar, Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '04) Oct. 2004.
   
• A Reliability Odometer - Lemon Check Your Processor, J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, Wild and Crazy Ideas Session at the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), October 2004.
   
• JSR 133: Java Memory Model and Thread Specification, July 2004. This is the product of the expert group for the Java Specification Request 133. The primary technical authors are: J. Manson, W. W. Pugh, and S. V. Adve.
   
• The Impact of Technology Scaling on Lifetime Reliability, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, Proceedings of International Conference on Dependable Systems and Networks (DSN '04) June 2004.
   
• The Energy Efficiency of CMP vs. SMT for Multimedia Workloads , R. Sasanka, S. V. Adve, Y. -K. Chen, and E. Debes, Proceedings of the 18th Annual ACM International Conference on Supercomputing (ICS '04) June 2004.
   
• The Case for Lifetime Reliability-Aware Microprocessors, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, Proceedings of 31st International Symposium on Computer Architecture (ISCA '04) June 2004.
   
• A Formal Approach to Frequent Energy Adaptations for Multimedia Applications, Christopher J. Hughes and Sarita V. Adve, Proceedings of 31st International Symposium on Computer Architecture (ISCA '04) June 2004.
   
• GRACE: A Hierarchical Adaptation Framework for Saving Energy, D.G. Sachs, W. Yuan, C.J. Hughes, A. Harris, S.V. Adve, D.L. Jones, R.H. Kravets, and K. Nahrstedt, Department of Computer Science, University of Illinois Technical Report UIUCDCS-R-2004-2409, February 2004.
   
• GRACE: A Cross-Layer Adaptation Framework for Saving Energy, D. G. Sachs, W. Yuan, C. J. Hughes, A. F. Harris, S. V. Adve, D. L. Jones, R. H. Kravets, and K. Nahrstedt, Sidebar in IEEE Computer, special issue on Power-Aware Computing, December 2003, 50-51.
   
• Adaptive Video Coding to Reduce Energy on Adaptive General-Purpose Processors, D. G. Sachs, S. Adve, D. L. Jones, Proceedings of the International Conference on Image Processing 2003 (ICIP '03), September 2003.
   
• Predictive Dynamic Thermal Management for Multimedia Applications , Jayanth Srinivasan and Sarita V. Adve, Proceedings of the 17th Annual ACM International Conference on Supercomputing (ICS '03) June 2003, 109-120. See correction in WDDD'05.
   
• Design and Evaluation of A Cross-Layer Adaptation Framework for Mobile Multimedia Systems, Wanghong Yuan, Klara Nahrstedt, Sarita V. Adve, Douglas L. Jones, and Robin H. Kravets, Proceedings of the SPIE Conference on Multimedia Computing and Networking, January 2003.
   
• Soft Real-Time Scheduling on a Simultaneous Multithreaded Processor, R. Jain, C. J. Hughes, and S. V. Adve, Proceedings of the 23rd IEEE International Real-Time Systems Symposium (RTSS-2002), December 2002.
   
• Joint Local and Global Hardware Adaptations for Energy, Ruchira Sasanka, Christopher J. Hughes, and Sarita V. Adve, Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.
   
• The Illinois GRACE Project: Global Resource Adaptation through CoopEration, Sarita V. Adve, Albert F. Harris, Christopher J. Hughes, Douglas L. Jones, Robin H. Kravets, Klara Nahrstedt, Daniel Grobe Sachs, Ruchira Sasanka, Jayanth Srinivasan, and Wanghong Yuan, Proceedings of the Workshop on Self-Healing, Adaptive, and self-MANaged Systems (SHAMAN) (held in conjunction with the 16th Annual ACM International Conference on Supercomputing), June 2002.
• RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors, C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, IEEE Computer, vol. 35, no. 2, special issue on high performance simulators, February 2002, 40-49.
   
• Performance Simulation Tools, S. S. Mukherjee, S. V. Adve, T. Austin, J. Emer, and P. S. Magnusson, IEEE Computer, vol. 29, no. 12, guest editors' introduction to the special issue on high performance simulators, February 2002, 38-39.
   
• Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications, C. J. Hughes, J. Srinivasan, and S. V. Adve, Proceedings of the 34th International Symposium on Microarchitecture (MICRO-34), December 2001, 250-261. Click here for supplemental data.
• Position Paper for NSF Workshop on Computer Performance Evaluation, S. V. Adve, December 2001.
• Comparing and Combining Read Miss Clustering and Software Prefetching, V. S. Pai and S. V. Adve, Proceedings of the International Symposium on Parallel Architectures and Compilation Techniques, September 2001, 292-303.
• Variability in the Execution of Multimedia Applications and Implications for Architecture, C. J. Hughes, P. Kaul, S. V. Adve, R. Jain, C. Park, and J. Srinivasan, Proceedings of the 28th International Symposium on Computer Architecture, June 2001, 254-265.
• Reconfigurable Caches and their Application to Media Processing, P. Ranganathan, S. V.Adve, and N. P. Jouppi, Proceedings of the 27th International Symposium on Computer Architecture, June 2000, 214-224.
• Code Transformations to Improve Memory Parallelism , V. S. Pai and S. V. Adve, The Journal of Instruction Level Parallelism, special issue on the best papers from MICRO-32, vol. 2, May 2000 (http://www.jilp.org/vol2). A shorter version of this paper appeared in the Proceedings of the 32nd International Symposium on Microarchitecture (MICRO-32), November 1999, 147-155.
• Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions , P. Ranganathan, S. V. Adve, and N. P. Jouppi, Proceedings of the 26th International Symposium on Computer Architecture, May 1999, 124-135.
• Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors, M. Durbhakula, V. S. Pai, and S. V. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, January 1999, 23-32. An extended version with some additional data appears as Technical Report #9802, Department of Electrical and Computer Engineering, Rice University, April 1998, revised December 1998.
• The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors , V. S. Pai, P. Ranganathan, H. Abdel-Shafi, and S. V. Adve, IEEE Transactions on Computers, special issue on caches, vol. 48, no. 2, February 1999, 218-226.
• Recent Advances in Memory Consistency Models for Hardware Shared-Memory Systems, , S. V. Adve, V. S. Pai, and P. Ranganathan, Proceedings of the IEEE, special issue on distributed shared-memory, vol. 87, no. 3, March 1999, 445-455.
• Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors, P. Ranganathan, K. Gharachorloo, S. V. Adve, and L. A. Barroso, Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems,October 1998, 307-318.
• Analytic Evaluation of Shared-Memory Systems with ILP Processors , D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, Proceedings of the 25th International Symposium on Computer Architecture, June 1998, 380-391.
• A Customized MVA Model for ILP Multiprocessors , D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve, and D. A. Wood, Technical Report #1369, Computer Sciences Department, University of Wisconsin -- Madison, April 1998. Also available as Technical Report #9803, Department of Electrical and Computer Engineering, Rice University. (Provides details of the model discussed in the ISCA'98 paper above.)
• Using Information From the Programmer to Implement System Optimizations Without Violating Sequential Consistency, S.V. Adve, Provisionally accepted for the Journal of Parallel and Distributed Computing (JPDC). Available as Rice University ECE Technical Report 9603, March 1996, revised June 1998. 
• A Retrospective on "Weak Ordering -- A New Definition", S. V. Adve and M. D. Hill, 25 Years of the International Symposia on Computer Architecture - Selected Papers (Gurindar S. Sohi, editor), ACM Press, 1998.
• Changing Interaction of Compiler and Architecture , S.V. Adve, D.C. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith, C.H. Gebotys, M.T. Kandemir, D.J. Lilja, A.N. Choudhary, J.Z. Fang, and P.-C. Yew, IEEE Computer, 30 (12), December 1997, 51-58.
• RSIM Reference Manual Version 1.0 , Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Technical Report 9705, Department of Electrical and Computer Engineering, Rice University, August 1997.
• Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models , Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve, Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, June 1997, 199-210. (pdf)
• RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, IEEE Technical Committee on Computer Architecture newsletter, Fall 1997. An earlier version of this paper appeared in the Proceedings of the 3rd Workshop on Computer Architecture Education (held in conjunction with the 3rd International Symposium on High Performance Computer Architecture), February 1997.
• The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems, Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, and Sarita V. Adve, Proceedings of the 24th International Symposium on Computer Architecture, June 1997, 144-156.
• An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors, Hazim Abdel-Shafi, Jonathan Hall, Sarita V. Adve, and Vikram S. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, February 1997, 204-215.
• The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Proceedings of the 3rd International Symposium on High Performance Computer Architecture, February 1997, 72-83.
• Shared Memory Consistency Models: A Tutorial, S.V. Adve and K. Gharachorloo, IEEE Computer, December 1996, 66-76.
• An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), October 1996, 12-23.
• A Comparison of Entry Consistency and Lazy Release Consistency Implementations, S.V. Adve, A.L. Cox, S. Dwarkadas, R. Rajamony, and W. Zwaenepoel, Proceedings of the 2nd International Symposium on High Performance Computer Architecture, February 1996, 26-37.
• Replacing Locks by Higher-Level Primitives, S.V. Adve, A.L. Cox, S. Dwarkadas, and W. Zwaenepoel, Technical Report #TR94-237, Department of Computer Science, Rice University, 1994. Presented at the Fourth Workshop on Scalable Shared-Memory Multiprocessors, Chicago, May 1994.
• Designing Memory Consistency Models for Shared-Memory Multiprocessors, S. V. Adve, Ph.D. Thesis, Available as Computer Sciences Technical Report #1198, University of Wisconsin, Madison, December 1993.
• Specifying System Requirements for Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Technical Report #CSL-TR-93-594, Stanford University, December 1993. Also available as Computer Sciences Technical Report #1199, University of Wisconsin, Madison, December 1993.
• Sufficient System Requirements for Supporting the PLpc Memory Model, S.V. Adve, K. Gharachorloo, A. Gupta, J.L. Hennessy, and M.D. Hill, Computer Sciences Technical Report #1200, University of Wisconsin, Madison, December 1993. Also available as Technical Report #CSL-TR-93-595, Stanford University, December 1993.
• A Unified Formalization of Four Shared-Memory Models, S.V. Adve and M.D. Hill, IEEE Transactions on Parallel and Distributed Systems 4, 6 (June 1993), 613-624.
• Sufficient Conditions for Implementing the Data-Race-Free-1 Memory Model, S.V. Adve and M.D. Hill, Computer Sciences Technical Report #1107, University of Wisconsin, Madison, September 1992.
• Programming for Different Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Journal of Parallel and Distributed Computing, August 1992, 399-407.
• Comparison of Hardware and Software Cache Coherence Schemes, S.V. Adve, V.S. Adve, M.D. Hill, and M.K. Vernon, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 298-308. Also appears in The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions, edited by Milo Tomasevic and Veljko Milutinovic, IEEE Computer Society Press, 1993. An extended version appears in Computer Sciences Technical Report #1012, University of Wisconsin, Madison, March 1991.
• Detecting Data Races on Weak Memory Systems, S.V. Adve, M.D. Hill, B.P. Miller, and R.H.B. Netzer, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 234-243.
• Weak Ordering - A New Definition, S.V. Adve and M.D. Hill, Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990, 2-14.
• Implementing Sequential Consistency in Cache-Based Systems, S.V. Adve and M.D. Hill, Proceedings of the 1990 International Conference on Parallel Processing, August 1990, I47-I50.

Talks

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• ILLIXR: An Open Testbed to Enable Extended Reality Systems Research, Sarita Adve. Sandia National Labs 4th Annual XR conference, July 2022. Also given at the Hot3D session at High Performance Graphics, July 2022. Video.


• Systems 2030: The Extended Reality Case, Sarita Adve. University of Washington Distinguished Lecture Series, February 2021. Video.


• Towards Princepled Error-Efficient Systems, Sarita Adve. IOLTS, July 2020.


• Epochs: Efficient Programmability of Cognitive Heterogeneous Systems, Sarita Adve. ERI Summit, July 2019. Video


• gem5-Approxilyzer: An Open-Source Tool for Application-Level Soft Error Analysis, Radha Venkatagiri. IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2019.


• I-USHER: Interfaces to Unlock the Specialized HardwarE Revolution, Sarita V. Adve. Outbrief to DARPA on a DARPA/ISAT study, April 2019.


• The Changing Face of Computing, Sarita V. Adve, IIT-Bombay Techfest Lecture Series, December 2018.


• Memory Consistency Models: They are Broken and Why We Should Care, Sarita V. Adve, Ken Kennedy Award Lecture, November 2018. Video


• HeteroSync: A Benchmark Suite for Fine-Grained Synchronization on Tightly Coupled GPUs, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, to appear in the IEEE International Symposium on Workload Characterization (IISWC), October 2017.


• Spandex: A Flexible Interface for Efficient Heterogeneous Coherence, at International Symposium on Computer Architecture (ISCA), June 2018. Lightning Talk
• Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, at International Symposium on Computer Architecture (ISCA), June 2017. Lightning Talk
• Coherence, Consistency, and Deja vu: Memory Hierarchies in the Era of Specialization, Keynote talk at the High Performance and Embedded Architecture and Compilation conference (HiPEAC), January 2017. Video.
• Approxilyzer: Towards A Systematic Framework for Instruction-Level Approximate Computing and its Application to Hardware Resiliency, at 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2016
• GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs, at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
• DeNovo: Energy-Efficient Memory Hierarchy for Heterogeneous Systems, at TI, January 2016.
• Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models, at 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2015. Lightning Talk
• Debunking or Deconstructing the End of Moore's Law, Panelist, WDDD'15, held in conjunction with ISCA'15, Portland, June 2015.
• Stash: Have Your Scratchpad and Cache it Too, at International Symposium on Computer Architecture (ISCA), June 2015.
• Stash: Have Your Scratchpad and Cache it Too, Ecole Polytechnique Federale de Lausanne, April 2015.
• Approximate Computing: (Old) Hype or New Frontier?, keynote at the 2nd Annual WACAS, March 2015.
• DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations, at ASPLOS 2015, March 2015.
• Eliminating On-Chip Traffic Waste: Are We There Yet?, at IEEE International Symposium on Performance Analysis of Systems and Software, March 2015.
   
• Revisiting the Complexity of Hardware Cache Coherence and Some Implications, at High Performance and Embedded Architecture and Compilation, January 2015.
• Hardware Fault Recovery for I/O Intensive Applications,at High Performance and Embedded Architecture and Compilation, January 2015.
• DeNovo: A Software-Driven Rethinking of the Memory Hierarchy,at Ecole Polytechnique Federale de Lausanne, September 2014.
• Stash: Have Your Scratchpad and Cache it Too, at NVIDIA Research, July 2014.
• Exploiting Software Information for an Efficient Memory Hierarchy, at Cavium Networks, July 2014.
• GangES: Gang Error Simulation for Hardware Resiliency Evaluation, at International Symposium on Computer Architecture (ISCA), June 2014.
• Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- San Diego, June 2014.
• Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- Raleigh, June 2014.
• Exploiting Software Information for an Efficient Memory Hierarchy, at Oracle Labs, April 2014.
• DeNovo: A Software Driven Rethinking of the Memory Hierarchy, at University of Wisconsin-Madison, February 2014.
• Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures, at Qualcomm Research, September 2013.
• Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures, at Qualcomm Research, May 2013.
• DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism at ASPLOS 2013, March 2013.
• The Imperative of Disciplined Parallelism: A Hardware Architect's Perspective. Keynote at the 4th Workshop on Determinism and Correctness in Parallel Programming (WoDet), held with ASPLOS'13, March 2013.
• Rethinking Parallel Languages and Hardware. Distinguished lecture series at the University of Toronto, March 2013.
• DeNovo: A Software-Driven Rethinking of the Memory Hierarchy. At ASPLOS PC symposium, University of California at Berkeley, October 2012.
• SWAT: SoftWare Anomaly Treatment. At DOE (ICiS) sponsored workshop titled "Addressing Failures in Exascale Computing," August 2012.
• Hardware-Level Reliability Does Not Matter in the Data Centre. Panelist at Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2012.
• Acceptance speech at the Anita Borg Institute Women of Vision awards ceremony, May 2012.
• DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism in the best paper session of PACT 2011, October 2011.
• Rethinking Shared-Memory Languages and Hardware, keynote at ICS, June 2011. Here is a video of a similar talk given at the Triangle distinguished lecture series, Duke University, April 2011.
• DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism in the "UPCRC Seminar", sponsored by Intel and Microsoft, December 2010.
• SWAT: A Complete Solution for In-Core Fault Resiliency in "GSRC eSeminar series", October 2010.
• Semantics of Shared Variables and Synchronization a.k.a. Memory Models , tutorial by S. V. Adve and H.-J. Boehm at PLDI, June 2010.
• DeNovo: Rethinking Hardware for Disciplined Parallelism in the "UPCRC Illinois Summit", sponsored by Intel and Microsoft, March 2010.
• Rethinking Hardware and Software for Disciplined Parallelism, in the "Advancing Computer Architecture Research" workshop sponsored by CRA/CCC, Feb 2010.
• Memory Models: A Case for Rethinking Parallel Languages and Hardware, a distinguished lecture by Sarita Adve at the University of Michigan, Feb 2010.
• SWAT: Designing Resilient Hardware by Treating Software Anomalies, an invited talk by Sarita Adve at the University of Michigan, Feb 2010. Versions of this talk have been given at various places, including Wisconsin, Intel, and various GSRC meetings.
• Memory Models: A Case for Rethinking Parallel Languages and Hardware, keynote talk at a plenary session of PODC and SPAA, Aug 2009.

Ph.D. Theses

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• Design and Evaluation of Extended Reality Systems, Muhammad Huzaifa, 2022.  
• Towards Scalable and Specialized Application Error Analysis, Abdulrahman Mahmoud, 2020.  
• Democratizing Error-Efficient Computing, Radha Venkatagiri, 2020.  
• Specialization Without Complexity in Heterogeneous Memory Systems, John Alsop, 2018.  
• Efficient Coherence and Consistency for Specialized Memory Hierarchies, Matthew Sinclair, 2017.  
• DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism, Hyojin Sung, 2015.  
• Exploiting Software Information for an Efficient Memory Hierarchy, Rakesh Komuravelli, 2014.  
• Preserving Application Reliability on Unreliable Hardware, Siva Kumar Sastry Hari, 2013.  
• Detecting and Recovering from In-core Hardware Faults through Software Anomaly Treatment, Pradeep Ramachandran, 2011.  
• SWAT: Designing Resilient Hardware by Treating Software Anomalies, Man-Lap (Alex) Li, 2009.  
• Soft Error Modeling And Analysis for Microprocessors, Xiaodong (Jerry) Li, 2008.  
• Lifetime Reliability Aware Microprocessors , Jayanth Srinivasan, 2006.  
• ALP: Energy Efficient Support for All Levels of Parallelism for Complex Media Applications, Ruchira Sasanka, 2005.  
• General-Purpose Processors for Multimedia Applications: Predictability and Energy Efficiency, Christopher Hughes, 2003.  
• Exploiting Instruction-Level Parallelism for Memory System Performance, Vijay Pai, 2000  
• General-Purpose Architectures for Media Processing and Database Workloads, Parthasarathy Ranganthan, 2000.  
• Designing Memory Consistency Models for Shared-Memory Multiprocessors, Sarita V. Adve, Available as Computer Sciences Technical Report #1198, University of Wisconsin, Madison, December 1993.

M.S. Theses

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• ILLIXR-A: An Open Source Extended Reality System for Android Platforms, Madhuparna Bhowmik, 2023  
• Hardware Implementation and Evaluation of the Spandex Cache Coherence Protocol, Zeran Zhu, 2021  
• Relyzer+: An Open Source Tool for Application-Level Soft Error Resiliency Analysis, Khalique Ahmed, 2018  
• Intelligent Scheduling for Simultaneous CPU-GPU Applications, Lin Cheng, 2017  
• GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs, Johnathan Alsop, 2016  
• Eliminating On-Chip Traffic Waste: Are We There Yet?, Robert Smolinski, 2013  
• Verification and Performance of the DeNovo Cache Coherence Protocol, Rakesh Komuravelli, 2010  
• Low-cost Hardware Fault Detection and Diagnosis for Multicore Systems Running Multithreaded Workloads, Siva Kumar Sastry Hari, 2009  
• Limitations of the MTTF metric for architecture-level lifetime reliability analysis, Pradeep Ramachandran, 2007  
• Data-Level and Thread-Level Parallelism in Emerging Multimedia Applications, Man-Lap (Alex) Li, 2005  
• Integrated Global and Per-Application Cross-Layer Adaptations for Saving Energy, Vibhore Vardhan, 2004  
• Joint Processor-Memory Adaptation for Energy for General-Purpose Applications, Ritu Gupta, 2004  
• Architectural Adaptation for Thermal Control, Jayanth Srinivasan, 2002  
• Combining Intra-Frame with Inter-Frame Hardware Adaptations to Save Energy, Ruchira Sasanka, 2002  
• Soft Real-Time Scheduling on a Simultaneous Multithreaded Processor, Rohit Jain, 2002  
• Variability in the Execution of Multimedia Applications and Implications for Architecture, Praful Kaul, 2002  
• Prefetching Linked Data Structures in Systems with Merged DRAM-Logic, Chris J. Hughes, 2002  
• Improving the Speed vs. Accuracy Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors, S. Murthy Durbhakula, 1998  
• Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors, Hazim Abdel-Shafi, 1997  
• The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology, Vijay Pai, 1997  
• An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Parthasarathy Ranganathan, 1997