RSIM Group Publications

RSIM Home

People

Research Projects

4-PEAKS

GRACE

RSIM Simulator

RSIM Project (old)

Memory Models (old)

Papers

Software

Funding

RSIM Group Publications

Refereed Publications and Current Submissions

Other Publications

Ph.D. Theses

M.S. Theses

Refereed Publications and Current Submissions

Adaptive Video Coding to Reduce Energy on Adaptive General-Purpose Processors, D. G. Sachs, S. Adve, D. L. Jones, to appear in the Proceedings of the International Conference on Image Processing 2003 (ICIP '03), Barcelona, Spain, September 2003.
Predictive Dynamic Thermal Management for Multimedia Applications, Jayanth Srinivasan and Sarita V. Adve, Proceedings of the 17th Annual ACM International Conference on Supercomputing (ICS03) June 2003, 109-120.
Design and Evaluation of A Cross-Layer Adaptation Framework for Mobile Multimedia Systems, Wanghong Yuan, Klara Nahrstedt, Sarita V. Adve, Douglas L. Jones, and Robin H. Kravets, Proceedings of the SPIE Conference on Multimedia Computing and Networking, January 2003.
Soft Real-Time Scheduling on a Simultaneous Multithreaded Processor, R. Jain, C. J. Hughes, and S. V. Adve, Proceedings of the 23rd IEEE International Real-Time Systems Symposium (RTSS-2002), December 2002.
Joint Local and Global Hardware Adaptations for Energy, Ruchira Sasanka, Christopher J. Hughes, and Sarita V. Adve, To appear in the Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.
The Illinois GRACE Project: Global Resource Adaptation through CoopEration, Sarita V. Adve, Albert F. Harris, Christopher J. Hughes, Douglas L. Jones, Robin H. Kravets, Klara Nahrstedt, Daniel Grobe Sachs, Ruchira Sasanka, Jayanth Srinivasan, and Wanghong Yuan, Proceedings of the Workshop on Self-Healing, Adaptive, and self-MANaged Systems (SHAMAN) (held in conjunction with the 16th Annual ACM International Conference on Supercomputing), June 2002.
RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors, C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, IEEE Computer, vol. 35, no. 2, special issue on high performance simulators, February 2002, 40-49.
Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications, C. J. Hughes, J. Srinivasan, and S. V. Adve, Proceedings of the 34th International Symposium on Microarchitecture (MICRO-34), December 2001, 250-261. Click here for supplemental data.
Comparing and Combining Read Miss Clustering and Software Prefetching, V. S. Pai and S. V. Adve, Proceedings of the International Symposium on Parallel Architectures and Compilation Techniques, September 2001, 292-303.
Variability in the Execution of Multimedia Applications and Implications for Architecture, C. J. Hughes, P. Kaul, S. V. Adve, R. Jain, C. Park, and J. Srinivasan, Proceedings of the 28th International Symposium on Computer Architecture, June 2001, 254-265.
Memory Side Prefetching for Linked Data Structures, C. J. Hughes and S. V. Adve. Provisionally accepted (subject to minor revisions) for the Journal of Parallel and Distributed Computing (JPDC). Available as Department of Computer Science Technical Report UIUCDCS-R-2001-2221, University of Illinois at Urbana-Champaign, May, 2001.
Reconfigurable Caches and their Application to Media Processing, P. Ranganathan, S. V.Adve, and N. P. Jouppi, Proceedings of the 27th International Symposium on Computer Architecture, June 2000, 214-224.
Code Transformations to Improve Memory Parallelism , V. S. Pai and S. V. Adve, The Journal of Instruction Level Parallelism, special issue on the best papers from MICRO-32, vol. 2, May 2000 (http://www.jilp.org/vol2). A shorter version of this paper appeared in the Proceedings of the 32nd International Symposium on Microarchitecture (MICRO-32), November 1999, 147-155.
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions , P. Ranganathan, S. V. Adve, and N. P. Jouppi, Proceedings of the 26th International Symposium on Computer Architecture, May 1999, 124-135.
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors, M. Durbhakula, V. S. Pai, and S. V. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, January 1999, 23-32. An extended version with some additional data appears as Technical Report #9802, Department of Electrical and Computer Engineering, Rice University, April 1998, revised December 1998.
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors , V. S. Pai, P. Ranganathan, H. Abdel-Shafi, and S. V. Adve, IEEE Transactions on Computers, special issue on caches, vol. 48, no. 2, February 1999, 218-226.
Recent Advances in Memory Consistency Models for Hardware Shared-Memory Systems, , S. V. Adve, V. S. Pai, and P. Ranganathan, Proceedings of the IEEE, special issue on distributed shared-memory, vol. 87, no. 3, March 1999, 445-455.
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors, P. Ranganathan, K. Gharachorloo, S. V. Adve, and L. A. Barroso, Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems,October 1998, 307-318.
Analytic Evaluation of Shared-Memory Systems with ILP Processors , D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, Proceedings of the 25th International Symposium on Computer Architecture, June 1998, 380-391.
Using Information From the Programmer to Implement System Optimizations Without Violating Sequential Consistency, S.V. Adve, Provisionally accepted for the Journal of Parallel and Distributed Computing (JPDC). Available as Rice University ECE Technical Report 9603, March 1996, revised June 1998.
Changing Interaction of Compiler and Architecture , S.V. Adve, D.C. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith, C.H. Gebotys, M.T. Kandemir, D.J. Lilja, A.N. Choudhary, J.Z. Fang, and P.-C. Yew, IEEE Computer, 30 (12), December 1997, 51-58.
Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models , Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve, Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, June 1997, 199-210.
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems, Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, and Sarita V. Adve, Proceedings of the 24th International Symposium on Computer Architecture, June 1997, 144-156.
An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors, Hazim Abdel-Shafi, Jonathan Hall, Sarita V. Adve, and Vikram S. Adve, Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, February 1997, 204-215.
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodolgy, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Proceedings of the 3rd International Symposium on High Performance Computer Architecture, February 1997, 72-83.
Shared Memory Consistency Models: A Tutorial, S.V. Adve and K. Gharachorloo, Rice University ECE Technical Report 9512 and Western Research Laboratory Research Report 95/7, September 1995. A version of this paper appears in IEEE Computer, December 1996, 66-76.
An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), October 1996, 12-23.
A Comparison of Entry Consistency and Lazy Release Consistency Implementations, S.V. Adve, A.L. Cox, S. Dwarkadas, R. Rajamony, and W. Zwaenepoel, Proceedings of the 2nd International Symposium on High Performance Computer Architecture, February 1996, 26-37.
A Unified Formalization of Four Shared-Memory Models, S.V. Adve and M.D. Hill, IEEE Transactions on Parallel and Distributed Systems 4, 6 (June 1993), 613-624.
Programming for Different Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Journal of Parallel and Distributed Computing, August 1992, 399-407.
Comparison of Hardware and Software Cache Coherence Schemes, S.V. Adve, V.S. Adve, M.D. Hill, and M.K. Vernon, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 298-308. Also appears in The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions, edited by Milo Tomasevic and Veljko Milutinovic, IEEE Computer Society Press, 1993. An extended version appears in Computer Sciences Technical Report #1012, University of Wisconsin, Madison, March 1991.
Detecting Data Races on Weak Memory Systems, S.V. Adve, M.D. Hill, B.P. Miller, and R.H.B. Netzer, Proceedings of the 18th Annual International Symposium on Computer Architecture, May 1991, 234-243.
Weak Ordering - A New Definition, S.V. Adve and M.D. Hill, Proceedings of the 17th Annual International Symposium on Computer Architecture, May 1990, 2-14.
Implementing Sequential Consistency in Cache-Based Systems, S.V. Adve and M.D. Hill, Proceedings of the 1990 International Conference on Parallel Processing, August 1990, I47-I50.

Other Publications

GRACE: A Hierarchical Adaptation Framework for Saving Energy, D.G. Sachs, W. Yuan, C.J. Hughes, A. Harris, S.V. Adve, D.L. Jones, R.H. Kravets, and K. Nahrstedt, Department of Computer Science, University of Illinois Technical Report UIUCDCS-R-2004-2409, February 2004.
Performance Simulation Tools, S. S. Mukherjee, S. V. Adve, T. Austin, J. Emer, and P. S. Magnusson, IEEE Computer, vol. 29, no. 12, guest editors' introduction to the special issue on high performance simulators, February 2002, 38-39.
A Retrospective on "Weak Ordering -- A New Definition", S. V. Adve and M. D. Hill, 25 Years of the International Symposia on Computer Architecture - Selected Papers (Gurindar S. Sohi, editor), ACM Press, 1998.
A Customized MVA Model for ILP Multiprocessors , D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve, and D. A. Wood, Technical Report #1369, Computer Sciences Department, University of Wisconsin -- Madison, April 1998. Also available as Technical Report #9803, Department of Electrical and Computer Engineering, Rice University. (Provides details of the model discussed in the ISCA'98 paper above.)
RSIM Reference Manual Version 1.0 , Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Technical Report 9705, Department of Electrical and Computer Engineering, Rice University, August 1997.
RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors, Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, IEEE Technical Committee on Computer Architecture newsletter, Fall 1997. An earlier version of this paper appeared in the Proceedings of the 3rd Workshop on Computer Architecture Education (held in conjunction with the 3rd International Symposium on High Performance Computer Architecture), February 1997.
Replacing Locks by Higher-Level Primitives, S.V. Adve, A.L. Cox, S. Dwarkadas, and W. Zwaenepoel, Technical Report #TR94-237, Department of Computer Science, Rice University, 1994. Presented at the Fourth Workshop on Scalable Shared-Memory Multiprocessors, Chicago, May 1994.
Designing Memory Consistency Models for Shared-Memory Multiprocessors, S. V. Adve, Ph.D. Thesis, Available as Computer Sciences Technical Report #1198, University of Wisconsin, Madison, December 1993.
Specifying System Requirements for Memory Consistency Models, K. Gharachorloo, S.V. Adve, A. Gupta, J.L. Hennessy, and M.D. Hill, Technical Report #CSL-TR-93-594, Stanford University, December 1993. Also available as Computer Sciences Technical Report #1199, University of Wisconsin, Madison, December 1993.
Sufficient System Requirements for Supporting the PLpc Memory Model, S.V. Adve, K. Gharachorloo, A. Gupta, J.L. Hennessy, and M.D. Hill, Computer Sciences Technical Report #1200, University of Wisconsin, Madison, December 1993. Also available as Technical Report #CSL-TR-93-595, Stanford University, December 1993.
Sufficient Conditions for Implementing the Data-Race-Free-1 Memory Model, S.V. Adve and M.D. Hill, Computer Sciences Technical Report #1107, University of Wisconsin, Madison, September 1992.