Memory Consistency Models

A memory consistency model for a shared-memory multiprocessor defines the order in which memory operations will appear to execute to a programmer, or in other words, the values a read may return [IEEE Computer tutorial]. 

Traditionally, memory consistency models have involved a significant tradeoff between performance (for the hardware and compiler) and programmability. My dissertation research (under Prof. Mark Hill at the University of Wisconsin-Madison) alleviates this tradeoff by showing how systems can use performance-enhancing techniques such as write buffers and out-of-order memory operations, but still allow programmers to reason with the simple model of sequential consistency.

As part of the RSIM project, I explored speculation techniques to narrow the hardware performance gap between sequential consistency (the simplest model) and relaxed memory consistency models [ASPLOS'96, SPAA'97, Proc. of the IEEE'99].

With the Rice Treadmarks group, I also worked on consistency models for software distributed shared-memory systems [HPCA'96].

I co-developed the Java memory model (adopted for Java 5.0 in 2005) and the default C++ memory model (currently in the process of standardization). Both are based on the foundation of data-race-free models proposed in my PhD thesis.




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