Processor simulation features:

• Multiple instruction issue
• Out-of-order scheduling
• Register renaming
• Static and dynamic branch prediction
• Non-blocking loads and stores
• Speculative load execution before prior stores are disambiguated
• Optimized memory consistency implementations

Memory simulation features:

• Two-level cache hierarchy
• Multiported and pipelined L1 cache, pipelined L2 cache
• Multiple outstanding cache requests
• Memory interleaving
• Software-controlled non-binding prefetching

Multiprocessor system features:

• CC-NUMA shared-memory system with directory-based coherence
• Support for MSI or MESI cache coherence protocols
• Support for sequential consistency, processor consistency, and release consistency
• Wormhole-routed mesh network

To the best of our knowledge, at the time of this release, RSIM is the only publicly available software for simulating shared-memory multiprocessors with state-of-the-art ILP processors. We have used RSIM in our research as well as in undergraduate and graduate courses in computer architecture.

• SUN machines running Solaris 2.5 or above
• SGI Power Challenge running IRIX 6.2
• Convex Exemplar running HP-UX version 10

Applications simulated on RSIM must be compiled and linked for SPARC V9/Solaris 2.5 or 2.6, and must be linked with the included library.

The RSIM Simulator and RSIM Utilities are available at no cost with the University of Illinois/NCSA open source license agreement.

The RSIM Applications Library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License.

To download RSIM version 1.0, please fill a brief registration form and indicate acceptance of the license agreements. If you redistribute RSIM in any way, we request that you let us know. We will be happy to include your URLs on our web site.

The RSIM Reference Manual is also separately available in Postscript (736 KB), Compressed postscript (225 KB), or HTML format. A more concise description of RSIM is available in Postscript (129 KB) or Compressed postscript (61 KB) format.

Hazim Abdel-Shafi, Murthy Durbhakula, Jonathan Hall, and Tracy Harton also contributed parts of the code and documentation.

Significant parts of the RSIM memory and network system are based on code from the Rice Parallel Processing Testbed (RPPT), a project led by Prof. J. R. Jump and Prof. J. B. Sinclair and involving several graduate students.