RSIM distribution -- Updates and Bugs

June 15, 2005 -- An x86 version of RSIM is available from the University of Murcia (Spain). Please contact Ricardo Fernandez Pascual at r.fernandez AT .

September 6, 2002 -- RSIM is now available with the UIUC/NCSA open source license

March 25, 1998 -- Release of SPLASH/SPLASH2 applications/kernels ported for RSIM. A few SPLASH/SPLASH2 applications/kernels ported for RSIM can be obtained by clicking on one of the following links: splash_apps.tar.gz (compressed, 3436 KB) or splash_apps.tar (uncompressed, 18915 KB).

The following lists known bugs in RSIM, with suggested fixes. Each bug report includes a short description of the bug and the suggested fix. Additionally, the bug report also classifies the bug into one of four classes based on the impact they could have on the results.

Attention, Solaris 2.6 users. We have had a couple of users write to us that they had problems when they compiled the applications using the newer Solaris version 2.6 libraries. Until the time we get to look at the code for the 2.6 libraries, it is recommended that all users continue to compile the applications with the Solaris 2.5 libraries

Compilation errors specific to some OS/Compiler vesions. Some OS/Compiler versions can occasionally produce compilation errors described in bug 25 and 26. If you get those errors, please use the fixes in the bug reports.

Bugs in RSIM version 1.0

Bugs in RSIM distributed from October 15, 1997 -- present
Bug #DescriptionAffectsReportedFixed
8Application problems with the solaris2.6 librarySolaris 2.6 users01/03/98outstanding
9Incorrect scheduling with in-order processorsUsers using in-order processor model10/15/9810/15/98
10Incorrect input/output handlingUsers using file input/output12/10/9812/10/98
11stdio.h macros incompatibility with gcc librariesUsers using file input/output macros12/10/9812/10/98
12Membar inconsistency in system calls Users using fread, sys_bzero, time, and times1/4/991/4/99
13Sign bit inconsistency in data forwardingUsers using conversion between signed/unsigned subword types1/4/991/4/99
14Problem with floating-point move conditional instructionsCodes with floating-point move conditional (generated by compiler in some cases)2/24/992/24/99
15Problem with write ancillary state register instructionCode with write ancillary state registers in which the 2nd source register was other than %g0 (not seen on any sample codes that run on RSIM distribution version)2/24/993/2/99
16Problem with multiplication for long long data typesCodes which use long long data type for 64-bit integer arithmetic3/10/993/11/99
17Double invocation of address generationApplications that stress the usage of the memory queue5/16/995/16/99
18Coherence protocol race in secondary cacheConfigurations with write-back L1 caches5/25/995/25/99
19Some directory output port full cases not handledApplications which stress directory outputs (affected code should seg-fault or die with error message)6/11/996/11/99
20Tree barriers assume power-of-2 number of processorsApplications run with non-power-of-2 number of processors3/21/983/21/98
21RSIM cannot run for more than 2 billion cyclesSome long-running applicationssummer '97outstanding
22Unnecessary warnings for directory codeNo impact (except for a few extra messages printed)6/21/996/21/99
23Typos in predecoderPossible impact if code includes SDIVcc or UDIVcc instructions with negative dividends10/22/9910/22/99
24Conflicting use of typedef and enum for ReqTypeLeads to errors with newer compilers10/22/9910/22/99
25Compliation errors for xor, dirname, new in,, FastNews.hLeads to compilation errors with some compilersSpring 03use suggested fix
26Unresolved symbols when compiling applications Leads to linker errors when building applications for RSIM on some OS verstions Spring03use suggested fix

Bugs in RSIM distributed from August 7, 1997 -- October 15, 1997:
Bug #DescriptionAffectsReportedFixed
1Unhandled race condition between L1 and L2 write-back cachesConfigurations with L1 write-back cache9/15/979/17/97
2Incorrect division of miss-type statistics (conflict vs. coherence)Cache miss breakdown statistics9/23/979/23/97
3Access out of array bounds in MESI state maintenance at MSHRsAll (no expected impact)9/25/979/25/97
4Javascript utility to generate configuration file reports spurious power-of-2 errors for number of cache setsConfigurations with small caches and high set associativity9/25/979/25/97
5Too much memory allocated in cache pipeline initializationAll (no impact)9/28/979/28/97
6Possible cache inclusion violation on L2 dirty writebacksConfigurations with L1 write-through caches10/2/9710/3/97
7Bus utilization statistics incorrectAll10/7/9710/7/97

RSIM bug classes

1Bug affects execution time, may need reruns
2Bug affects execution time, affects only runs that failed
3Bug does not affect execution time, affects only certain statistics
4Bug relating to portability of simulator to a different machine

RSIM bug mailing list

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