RSIM Reference Manual

Version 1.0

Vijay S. Pai

Parthasarathy Ranganathan

Sarita V. Adve

DEPT. OF ELECTRICAL AND COMPUTER ENGINEERING

RICE UNIVERSITY

6100 SOUTH MAIN

HOUSTON, TEXAS 77005

Email: rsim@cs.uiuc.edu

URL: http://rsim.cs.uiuc.edu/rsim rsim

TECHNICAL REPORT 9705

August 1997

• Contents
  • Overview
    • Key features of simulated systems
    • Simulation technique
    • Platforms supported
    • Applications interface
    • Future announcements and user feedback
    • Organization of this manual
• RSIM USER'S GUIDE
  • Installing RSIM
    • Unpacking the RSIM software distribution
    • Building the RSIM simulator
    • Building the RSIM applications library
    • Building applications ported to RSIM
      • Using the generic makefile
      • Using ordinary UNIX command sequences
    • Statistics processing utilities
  • Architectural Model
    • RSIM instruction set architecture
    • Processor microarchitecture
      • Pipeline stage details
      • Branch prediction
      • Processor memory unit
      • Exception handling
    • RSIM memory and network systems
  • Configuring RSIM
    • Command line options
      • Processor parameters
      • Memory unit parameters
      • Cache parameters
      • Approximate simulation models
      • Other architectural configuration parameters
      • Parameters related to simulation input/output
      • Simulator control and debugging
    • Configuration file
      • Overall system parameters
      • Processor parameters
      • Cache hierarchy parameters
      • Bus parameters
      • Directory and memory parameters
      • Interconnection network parameters
      • Queue sizes connecting memory and network modules
    • Compile-time parameters
  • Porting Applications to RSIM
    • Process creation and shared memory model
    • RSIM applications library
    • Synchronization support for multiprocessor applications
    • Statistics collection
    • Performance tuning
    • Options to improve simulation speed
      • Moving data initialization offline
      • Avoiding memory system simulation
  • Statistics Collection and Debugging
    • Statistics collection
      • Overall performance statistics
      • Processor statistics
      • Cache, network, and memory statistics
    • Utilities to process statistics
      • The stats and pstats programs
      • The plotall program
      • The stats_miss program
      • The MSHR program
    • Debugging
      • Support for debugging RSIM
      • Debugging applications
• RSIM DEVELOPER'S GUIDE
  • Overview of RSIM Implementation
  • Event-driven Simulation Library
    • Event-manipulation functions
    • Semaphore functions
    • Memory allocation functions
  • Initialization and Configuration Routines in RSIM
  • RSIM_EVENT and the Out-of-order Execution Engine
    • Overview of RSIM_EVENT
    • Instruction fetch and decode
    • Branch prediction
    • Instruction issue
    • Instruction execution
    • Completion
    • Graduation
    • Exception handling
    • Principal data structures
  • Processor Memory Unit
    • Adding new instructions to the memory unit
    • Address generation
    • Issuing instructions to the memory hierarchy
    • Completing memory instructions in the memory hierarchy
  • Memory Hierarchy and Interconnection System Fundamentals
    • Fundamentals of memory system modules
    • Memory system message data structure
      • The s.type field
      • The req_type field
      • The s.reply field
      • The s.nack_st field
    • Memory system simulator initialization
    • Deadlock avoidance
  • Cache Hierarchy
    • Bringing in messages
    • Processing the cache pipelines
    • Processing L1 cache actions
      • Handling REQUEST type
      • Handling REPLY type
      • Handling COHE type
    • Processing L2 tag array accesses
    • Processing L2 data array accesses
    • Cache initialization and statistics
    • Discussion of cache coherence protocol implementation
    • Coalescing write buffer
    • Deadlock avoidance
  • Directory and Memory Simulation
    • Obtaining a new or incomplete transaction to process
    • Processing incoming REQUESTs
    • Sending out COHE messages
    • Processing incoming write-back and replacement messages
    • Processing other incoming COHE_REPLYs
      • Handling positive acknowledgments
      • Handling negative acknowledgments
    • Deadlock avoidance
  • System Interconnects
    • Node bus
    • Network interface modules
    • Multiprocessor interconnection network
    • Deadlock avoidance
  • Statistics and Debugging Support
    • Statistics
    • Debugging Support
  • Implementation of predecode and unelf
    • The predecode utility
    • The unelf utility
• References
  • RSIM Version 1.0 License Terms and Conditions
• About this document ...