Source files: src/MemSys/wb.c, src/MemSys/wbuffer.c
Header files: incl/MemSys/cache.h
The coalescing write buffer is used in systems with a write-through L1 cache. Although the write buffer is conceptually in parallel with the L1 cache (Figure 3.2), the simulated module sits between the two caches. To provide the semblance of parallel access, the write buffer has zero delay.
The WBSim function implements the write buffer and is called from L2CacheOutSim (for REPLYs) and from L1CacheOutSim (for REQUESTs). This simulation module first checks for a message on any of its input queues. If one is available, the function jumps to the appropriate case to handle it.
If the incoming message is a REQUEST, it is handled according to
the req_type field of the message. If the request is a read type that does not match
any write in the buffer, it is immediately sent on to the L2 cache. If
the request is a read that does match a write in the buffer, the read
is stalled until the matching write issues from the write
buffer. This scheme follows the policy used in the Alpha 21164,
referred to as ``Flush-Partial'' in other
studies [21]
.
If the incoming REQUEST is a write, the write-buffer attempts to add it to the queue of outstanding write-buffer entries by calling the function notpres_wb. If the request matches the line of another outstanding write, it is coalesced with the previous write access. Each line conceptually includes a bit-vector to account for such coalescing. If there is no space for the write in the buffer, it is stalled until space becomes available. Writes are sent out of the write buffer and to the L2 cache as soon as space is available in the L2 input ports. This processing takes place in case 9 of the function WBSim. As soon as a write is added to an L2 port, its entry is freed from the write-buffer.
REPLYs are immediately forwarded to the L1 cache with no additional processing. The write buffer does not receive COHE or COHE_REPLY messages.