Source files: src/MemSys/setup_cohe.c
RSIM supports two coherence protocols - MSI and MESI. Both of these protocol implementations are depicted in Figure 3.3. In the MSI system, an explicit upgrade message is required for a read followed by a write, even if there are no other sharers. The MESI system overcomes this disadvantage. However, our MESI implementation requires a message to be sent to the directory on elimination of an exclusive line from the L2 cache. Some available MESI implementations avoid this replacement message; however, in such systems, the write-back of a modified line requires an acknowledgment from the memory controller and holds an entry in the write-back buffer until the reply arrives [12]. In our system, on the other hand, a write-back does not cause a reply, and the write-back buffer entry is freed as soon as the write-back issues to the ports below the cache. The bandwidth tradeoff between these two choices is application-dependent.