RSIM simulates two levels of data cache. The first-level of cache can be either write-through with no-write-allocate or write-back with write-allocate. The second-level cache is write-back with write-allocate and maintains inclusion of the first-level cache. Each cache supports multiple outstanding misses and is pipelined. The first-level cache may also be multiported. If the configuration uses a write-through L1 cache, a write-buffer is also included between the two levels of cache. The L1 cache tag and data access is modeled as a single access to a unified SRAM array, while an L2 cache access is modeled as an SRAM tag array access followed by an SRAM data array access. These arrays themselves are modeled as pipelines, processed by the functions in src/MemSys/pipeline.c
Like the processor, the cache hierarchy is activated by RSIM_EVENT function, which is scheduled to occur every cycle. RSIM_EVENT calls the functions L1CacheInSim, L2CacheInSim, L1CacheOutSim, and L2CacheOutSim for each cache, as mentioned in Section 10.1. Each of these functions, as well as the functions called by those functions, are described in this chapter.