Publications
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Specializing Coherence, Consistency, and Push/Pull for GPU Graph Analytics, Giordano Salvador, Wesley H. Darvin, Muhammad Huzaifa, Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve, in the proceedings of the 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) as an extended abstract.
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Spandex: A Flexible Interface for Efficient Heterogeneous Coherence, Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve, to appear in the 45th International Symposium on Computer Architecture (ISCA), June 2018.
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HeteroSync: A Benchmark Suite for Fine-Grained Synchronization on Tightly Coupled GPUs, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the IEEE International Symposium on Workload Characterization (IISWC), October 2017.
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Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve, in the 44th International Symposium on Computer Architecture (ISCA), June 2017.
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POSTER: hVISC: A Portable Virtual Instruction Set for Heterogeneous Parallel Systems, Prakalp Srivastava, Maria Kotsifakou, Matthew D. Sinclair, Rakesh Komuravelli, Vikram S. Adve, and Sarita V. Adve, in the 25th International Conference on Parallel Architecture and Compilation Techniques (PACT), September 2016.
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GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs, Johnathan Alsop, Matthew D. Sinclair, Rakesh Komuravelli, and Sarita V. Adve, in the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
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Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models,
Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve,
in the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) December 2015.
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Stash: Have Your Scratchpad and Cache it Too,
Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram Adve,
in the 42nd International Symposium on Computer Architecture (ISCA) May 2015.
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DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations,
Hyojin Sung and and Sarita V. Adve,
in the Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015.
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Eliminating On-Chip Traffic Waste: Are We There Yet?,
Robert Smolinski, Rakesh Komuravelli, Hyojin Sung, and Sarita V. Adve,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015. Find an extended version of the paper
here.
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Exploiting Software Information for an Efficient Memory Hierarchy,
Rakesh Komuravelli,
Ph.D. thesis, University of Illinois, Urbana-Champaign, 2014.
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Revisiting the Complexity of Hardware Cache Coherence and Some Implications,
Rakesh Komuravelli, Sarita V. Adve, and Ching-Tsun Chou,
in ACM Transactions on Architecture and Code Optimization (TACO),
December 2014.
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DeNovoND: Efficient Hardware Support for Disciplined Non-determinism,
Hyojin Sung, Rakesh Komuravelli, Sarita V. Adve,
in the Proceedings of 18th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS),
March 2013.
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Virtual Instruction Set Computing for Heterogeneous Systems,
Vikram Adve, Sarita Adve, Rakesh Komuravelli,
Matthew D. Sinclair, and Prakalp Srivastava,
4th USENIX Workshop on Hot Topics in Parallelism
(HotPar), June 2012.
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DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism,
Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, and Ching-Tsun Chou,
20th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2011, Best Paper Award.
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DeNovo: Rethinking Hardware for Disciplined Parallelism,
Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Bocchino, Sarita V. Adve, and Vikram S. Adve,
Second USENIX Workshop on Hot Topics in Parallelism (HotPar), 2010.
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Vector LLVA: A Virtual Vector Instruction Set for Media Processing,
Robert L. Bocchino Jr. and Vikram S. Adve,
Proceedings of the Second International Conference on Virtual Execution Environments (VEE '06), 2006.
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LLVA: A Low-level Virtual Instruction Set Architecture,
Vikram Adve, Chris Lattner, Michael Brukman, Anand Shukla and Brian Gaeke,
36th Annual International Sympoium on Microarchitecture, 2003.
Other Related Publications
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Secure Virtual Architecture: A Safe Execution Environment for Commodity Operating Systems,
John Criswell, Andrew Lenharth , Dinakar Dhurjati, and Vikram Adve,
Proceedings of the Twenty First ACM Symposium on Operating Systems Principles (SOSP '07), October 2007.
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Making Context-Sensitive Points-to Analysis with Heap Cloning Practical For The Real World,
Chris Lattner, Andrew Lenharth, and Vikram Adve,
Proc. of the 2007 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '07), June 2007.
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A Virtual Instruction Set Interface for Operating System Kernels,
John Criswell, Brent Monroe, and Vikram Adve,
Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA '06), 2006.
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Automatic Pool Allocation: Improving Performance by Controlling Data Structure Layout in the Heap,
Chris Lattner and Vikram Adve,
Proc. of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '05), June 2005.
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LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation, Chris Lattner and Vikram Adve,
Proc. of the 2004 International Symposium on Code Generation and Optimization (CGO '04), 2004.
Talks
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Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, at International Symposium on Computer Architecture (ISCA), June 2017. Lightning Talk
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Coherence, Consistency, and Deja vu: Memory Hierarchies in the Era of Specialization, Keynote talk
at the High Performance and Embedded Architecture and Compilation conference (HiPEAC), January 2017. Video.
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GSI: A GPU Stall Inspector to Characterize the Source of Memory Stalls for Tightly Coupled GPUs,
at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
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DeNovo: Energy-Efficient Memory Hierarchy for Heterogeneous Systems, at TI, January 2016.
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Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models, at 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2015. Lightning Talk
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Stash: Have Your Scratchpad and Cache it Too, at International Symposium on Computer Architecture (ISCA), June 2015.
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Stash: Have Your Scratchpad and Cache it Too, Ecole Polytechnique Federale de Lausanne, April 2015.
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DeNovoSync: Efficient Support for Arbitrary Synchronization without Writer-Initiated Invalidations, at ASPLOS 2015, March 2015.
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Eliminating On-Chip Traffic Waste: Are We There Yet?,
at IEEE International Symposium on Performance Analysis of Systems and Software, March 2015.
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Revisiting the Complexity of Hardware Cache Coherence and Some Implications, High Performance and Embedded Architecture and Compilation, January 2015.
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DeNovo: A Software-Driven Rethinking of the Memory Hierarchy,at Ecole Polytechnique Federale de Lausanne, September 2014.
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Stash: Have Your Scratchpad and Cache it Too, NVIDIA Research, July 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Cavium Networks, July 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- San Diego, June 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Qualcomm Research -- Raleigh, June 2014.
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Exploiting Software Information for an Efficient Memory Hierarchy, at Oracle Labs, April 2014.
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Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures,
at Qualcomm Research, September 2013.
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Addressing the Hardware Challenges of Tightly Coupled Heterogeneous Architectures,
at Qualcomm Research, May 2013.
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DeNovoND: Efficient Hardware Support for Disciplined Non-Determinism,
in ASPLOS 2013, March 2013.
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Virtual Instruction Set Computing for Heterogenous Systems (Teaser Presentation),
in HotPar 2012, June 2012.
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DeNovo: Rethinking the Multicore Memory Hierarchy for Disciplined Parallelism,
in the best paper session of PACT 2011, October 2011.
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