RSIM Bug Report #9

Version of RSIM1.0
Bug number9
Bug class1
Date10/15/98
Reported byInternal
AffectsUsers running in-order processor model
Filespipestages.cc

Problem Description

The variables that were keeping track of the outstanding instructions in an in-order processor model were being incorrectly modified. Consequently, an in-order processor had the potential to behave as an out-of-order processor in some cases.

Suggested work-around

The fix needs a change to one line of the code. Contact rsim@cs.uiuc.edu for details.