RSIM Bug Report #23
| Version of RSIM | 1.0 |
| Bug number | 23 |
| Bug class | 2 |
| Date | 10/22/99 |
| Reported by | authors |
| Affects | SPARC divide-with-condition code instructions (SDIVcc, UDIVcc) with negative dividends |
| Files | predecode_instr.cc |
Problem Description
The arith_3y function of the predecoder does not properly set
up the Y register as a source register of SDIVcc and
UDIVcc because of some typos. It seems that these
instructions are used less frequently in the compiler than
SDIV and UDIV, but they may still arise
nevertheless.
Problem Fix
In arith_3y, change all occurrences of SDIVcc and
UDIVcc to iSDIVcc and iUDIVcc,
respectively.
Thus, the code after the initial comments reads:
<![CDATA[
in->rd=Extract(undec,29,25);
in->rs1=Extract(undec,18,14);
if ((in->aux1 = Extract(undec,13,13)))
{
/* it's an immediate */
in->imm=SE(Extract(undec,12,0),13);
}
else
{
in->rs2=Extract(undec,4,0);
}
if (in->instruction == iSMUL || in->instruction == iUMUL)
{
in->rcc = STATE_Y;
}
if (in->instruction == iSDIV || in->instruction == iUDIV || in->instruction == iSDIVcc || in->instruction == iUDIVcc)
{
in->rscc = STATE_Y;
}
if (in->instruction == iSDIVcc || in->instruction == iUDIVcc)
{
in->rcc = COND_ICC;
}
return 1;
]]>