RSIM Bug Report #2

Version of RSIM1.0
Bug number2
Bug class3
Date9/23/97
Reported byauthors
AffectsCache-miss breakdown statistics
Filesl1cache.c, l2cache.c

Problem Description

The division of cache misses into capacity, conflict, and coherence misses in the multiprocessor case is currently incorrect. In files l1cache.c, and l2cache.c, the following code segment is called for all cache miss operations:

if (req->line_cold) { StatSet(captr,req,CACHE_MISS_COLD); } else { StatSet(captr,req,ccdres); } However, in cases of coherence misses, the previous variant of this code segment already updates the relevant statistics. Subsequently, all coherence misses are double counted. Note that this error occurs only with coherence misses, so the impact is less in up runs. Also note that the bug affects only the cache miss stats. The execution time and all other stats continue to remain the same.

Problem Fix

Move the above code segment into the else condition of the if (hittype == 1) construct. This has been updated in the new distribution versions of these cache files.