RSIM Bug Report #18

Version of RSIM1.0
Bug number18
Bug class2
Date5/25/99
Reported byauthors
AffectsConfigurations with write-back L1 cache
Filesl2cache.c

Problem Description

A certain coherence protocol race was not properly handled in the L2 cache code. In particular, inclusion could be violated if the L2 cache received the following sequence:
  1. Incoming external coherence message to line X
  2. Unsolicited L1 write-back of line X
  3. L1 request of line X
  4. L1 reply to external coherence message

Problem Fix

This required only a one-line fix in the COHE\_REPLY case of the function L2ProcessTagReq. One if-conditional in this case used to read:

/* NOTE: unmark cohe_pend for COHE_REPLY */ if (hittype == 0 && captr->data[i1][i2].state.cohe_pend) This should be replaced with:

/* NOTE: unmark cohe_pend for COHE_REPLY */ if (hittype == 0 && captr->data[i1][i2].state.cohe_pend && req->req_type != WRB)