This chapter describes fundamental aspects of the memory hierarchy, bus, and multiprocessor interconnection network implementation. We will refer to the implementation of these subsystems collectively as the memory system simulator. Subsequent chapters provide detailed investigations of each part of the memory system simulator.
Section 12.1 describes the various memory system simulator modules and their interconnection. Section 12.2 describes the essentials of the message data structure used to convey information within the memory system simulator (much as the instance data structure is used in the processor simulator). Section 12.3 describes the steps to construct the multiprocessor portion of the simulated architecture. Section 12.4 explains the steps taken throughout the memory system simulator to avoid deadlock.