Source files: src/Processor/graduate.cc
The graduate_cycle function controls the handling associated with graduation. First, the remove_from_active_list function is called. In this function, the processor looks at the head of the active list. If this operation completed in the previous cycle (and thus, has already had time to write its result into its register) and is not stalled for consistency constraints, the instruction is allowed to graduate from the active list. If an exception is detected, graduation is stopped and control is returned to graduate_cycle. If the instruction has no exception, then the old physical registers for its destinations are freed and the operation is graduated. As a simulator abstraction, RSIM also maintains a ``logical register file'', which stores committed values. This file is also updated at this time. The active list element is removed, and the instance is also freed for later use. remove_from_active_list repeats until the first operation in the active list is not ready to graduate, an exception is detected, or the processor's maximum graduation rate is reached. At that point, control is returned to graduate_cycle.
If remove_from_active_list returned an exception, the processor is put into exception mode and will handle the exception as soon as possible, without decoding or graduating any further instructions in the meantime.
graduate_cycle also calls mark_stores_ready. In this function, stores are marked ready to send data to the data cache if they are within the next set of instructions to graduate. Namely, the store must be no further from the head of the active list than the processor graduation rate, and all previous instructions must be completed and guaranteed free of exceptions. The store itself must also have its address ready and must not cause any exceptions; the only exception type currently detected at the time of mark_stores_ready is a segmentation fault (other exceptions would have already been detected). Note that this function considers stores primarily with regard to their effect on precise exceptions; even after being marked ready in this fashion, a store may still have to wait many cycles to issue due to store ordering constraints. In any system with nonblocking stores (PC, RC, or SC with the ``-N'' option), a store is considered ready to graduate as soon as it has been marked; it need not wait for issue or completion in the external memory system.