Source files: src/Processor/state.cc, src/Processor/pipestages.cc
RSIM_EVENT simulates the processors and cache hierarchies of the simulated system. It is scheduled every cycle as described in Chapter 7. On every invocation, RSIM_EVENT loops through all the processors and caches in the system, calling the functions described in this section.
Note that RSIM_EVENT should seek to process messages from other portions of the system without any unexpected or unnecessary delays. Suppose, for example, that the bus unit provided a reply to the L2 cache at time X. However, if the RSIM_EVENT planned for time X had already occurred, the RSIM_EVENT function would not be able to pick up the reply until time X+1. On the other hand, if the RSIM_EVENT function had not already been processed for the cycle, RSIM_EVENT would pick up the reply at time X. Thus, the timing behavior of the would be non-deterministic and could include unexpected delays. To avoid this sort of problem, RSIM_EVENT is actually scheduled to occur at an offset of 0.5 cycles from the processor cycle. RSIM_EVENT starts by completing operations that finished during the previous cycle, and then initiates new operations based on the current cycle.
For each processor, RSIM_EVENT first calls L1CacheOutSim and L2CacheOutSim (described in Section 13), which are used to process cache accesses. Then, CompleteMemQueue is called to inform the memory unit of any operations that have completed at the caches. CompleteQueues is used to process other instructions that have completed at their functional units.
Then, RSIM_EVENT calls maindecode. This function starts out by using update_cycle to update the register file and handle other issues involved with the completion stage of the pipeline. Next, graduate_cycle is called to remove previously completed instructions in-order from the active list and to commit their architectural state. Then, maindecode calls decode_cycle to bring new instructions into the active list. After this, maindecode returns control to RSIM_EVENT.
RSIM_EVENT then calls IssueQueues, which sends ready instructions to their functional units. After this, the functions L1CacheInSim and L2CacheInSim are called for the caches to bring in new operations that have been sent to them. After this, RSIM_EVENT loops on to the next processor.
Each of the functions mentioned above is more thoroughly discussed in the chapter related to its phase of execution. In particular, CompleteQueues, update_cycle, graduate_cycle, maindecode, decode_cycle, and IssueQueues are part of the out-of-order execution engine, which is discussed in the next several sections.