Overview of RSIM Implementation

 

The remainder of this manual describes the implementation of RSIM. It is intended for users interested in modifying RSIM, and assumes an understanding of Part i of this manual.

RSIM is organized as a discrete-event-driven simulator. The central data structure of such a simulator is an event list consisting of events that are scheduled for the future in simulation time. Typically, an event for a hardware module is scheduled for a given time only when it is known that the module will need to perform some action at that time. Thus, discrete-event-driven simulators typically do not perform an action for every cycle. In RSIM, however, the processors and cache hierarchies are modeled as a single event (called RSIM_EVENT), which is scheduled every cycle. This is because we expect that some activity will be required of the processor and caches every cycle. Note that RSIM is not a pure cycle-by-cycle simulator since events for the busses, directories, and network models are scheduled only when needed.

RSIM is implemented in a modular fashion for ease of development and maintenance. The primary subsystems in RSIM are the event-driven simulation library, the processor out-of-order execution engine, the processor memory unit, the cache hierarchy, the directory module, and the interconnection system. These modules perform the following roles:

Event-driven simulation library

Steers the course of the simulation, activating the processors, memory hierarchy, and network subsystem according to the demands of the simulated application and system. This subsystem is based on the YACSIM event-driven simulation library [3, 8].

Processor out-of-order execution engine

Maintains the processor pipelines described in Section 3.2.

Processor memory unit

Interfaces the processor pipelines with the caches, maintaining the various ordering constraints described in Section 3.2.3.

Cache hierarchy

Processes requests to the caches, including both demands from the processor and demands from external sources. A significant part of this subsystem is based on code from the RPPT (Rice Parallel Processing Testbed) direct-execution simulator.

Directory and memory module

Processes requests from various sources, maintaining the cache-coherence protocol of the system. This module is also based on code from RPPT.

Interconnection system

Connects the various modules within each node, and the nodes within the multiprocessor system. The multiprocessor interconnection network is based on the NETSIM simulation environment [7].

Each of the above subsystems acts as a largely independent block, interacting with the other units through a small number of predefined mechanisms. Thus, we expect most modifications to RSIM to be quite focussed, and affecting only the desired functionality. Our experience with RSIM in a classroom setting has borne these expectations out to some extent; however, each type of simulator change does require detailed knowledge of the subsytem being modified.

The remaining chapters in this part of the manual describe the above subsystems in detail and provide other additional information needed to understand the implementation of RSIM. Chapter 8 gives a brief explanation of the event-driven simulation library underlying RSIM and the manner in which RSIM uses it. Chapter 9 describes the initialization routines in RSIM. Chapter 10 gives an overview of RSIM_EVENT and describes the details of each stage in the processor out-of-order execution engine. Chapter 11 explains the implementation of the processor memory unit. Chapter 12 describes fundamental data structures used for the cache, memory, and network systems. Chapter 13 explains the key functions within the simulation of the cache hierarchy. Chapter 14 describes the implementation of the directory module. Chapter 15 explains the principles of the interconnection system simulated in RSIM. Chapter 16 explains the additional support provided by RSIM for statistics and debugging. Finally, Chapter 17 describes the RSIM predecoder and the unelf utility.