Processor parameters

 

-i num

Number of instructions to fetch in a cycle. Defaults to 4.

-a num

Active list size. Defaults to 64.

-g num

Maximum number of instructions to graduate per cycle. If the value 0 is given, then the processor will be able to graduate an unbounded number of instructions per cycle. Defaults to the same value as the instruction fetch width (specified in ``-i'', or 4 if no ``-i'' is given).

-u

Simulate fast functional units - all ALU and FPU instructions have single cycle latency. This option overrides any latencies specified in the configuration file.

-E num

Number of instructions to flush per cycle (from the active list) on an exception. If the value of 0 is given, the processor will flush all instructions immediately on an exception. Defaults to the same value as the graduation rate.

-q num,num

Many processors include one or more issue windows (corresponding to different sets of functional units) separate from the active list. These issue windows only hold instructions that have not yet issued to the corresponding functional units (or, in the case of memory instructions, instructions that have not completed all of their ordering constraints). Thus, the issue logic only needs to examine instructions in the corresponding windows for outstanding dependences. The ``-q'' option supports a processor that has separate issue windows for memory and non-memory instructions, and stalls further instruction decoding when a new instruction cannot obtain a space in its issue window. The first number specified with this option represents the size of the issue window for non-memory operations. The second number represents the size of the memory unit, and overrides any earlier use of the ``-m'' option below). Note that when ``-q'' is not used, the processor still supports a memory unit, but does not stall if the memory unit is full. This option has not yet been extensively tested. Unused by default.

-X

Static scheduling. Supported only with the straightforward implementation of release consistency. The static scheduling supported in RSIM includes register renaming and out-of-order completion. Memory instructions are considered issued once they have been sent to their address generation units; memory fences and structural hazards beyond that point may cause additional delays. This option has not yet been extensively tested. Unused by default.