RSIM provides a variety of debugging information for the developer looking to make changes to the system. Currently, the caches, bus, network interfaces, and directory have corresponding #defines which, when set at compile time, cause these modules to trace each of their important actions on the simulation output, along with information related to the specific access being considered. Any or all of these debugging options can be used at any time to trace the behavior of these modules. Additionally, the processor provides a variety of tracing information for each pipeline stage and each instruction execution if the COREFILE option is defined at compile-time. Each processor produces a trace file called corefile.i, where i is the unique identifier for the processor. The Makefile provided in the obj/dbg directory has all the common debugging options set so as to produce the maximum possible tracing output. Generally speaking, this is the desired level of tracing for most significant simulator changes.
In addition to this tracing provided by RSIM, RSIM can be run through any standard debugger. However, applications being simulated under RSIM cannot be debugged using a standard debugger from within the RSIM environment, as RSIM does not expose information about the application being simulated to the debugger.