Source files: src/MemSys/bus.c
Header files: incl/MemSys/bus.h
The RSIM bus module simulates an aggressive split-transaction bus that imposes no limits on outstanding requests. This bus connects the L2 cache, the network interfaces, and the directory/memory modules within a node. Arbitration is round-robin among the bus agents. As in a real system, a bus agent is not allowed to acquire the bus unless its destination is ready. The bus speed, bus width, and arbitration delays can be configured as described in Chapter 4.
The function node_bus represents the main operation of the bus simulator. This function is split up into several stages according to the progress of a request on the bus. In the BUSSTART stage, the bus has not started processing a transaction. In this case, the bus peeks at the ports round-robin (starting with the port after the one last accessed) for a new message. If a transaction is available, the bus moves to the SERVICE stage.
In the SERVICE stage, the routing function is called to determine the output port for this message. If that port is not available, the bus is delayed for a bus cycle before returning to BUSSTART, where it will try to find a different transaction or keep trying this transaction until the output becomes available. If the port is available, however, the bus transitions to the BUSDELIVER stage after stalling for the latency of the transfer (based on the message size, the bus width, and the bus cycle).
In the BUSDELIVER stage, the bus moves the transaction into the desired output port, after which it will stall for an arbitration delay before allowing BUSSTART to continue processing new requests.