Source files: src/MemSys/directory.c
Header files: incl/MemSys/directory.h
The processor and cache modules are simulated on a cycle-by-cycle basis, as these units are likely to have activity nearly every cycle. However, the remaining building blocks of RSIM are activated only according to whether or not they are ready to process a transaction.
The directory controller modeled in RSIM implements a 4-state MESI coherence protocol or a 3-state MSI protocol. The directory is merged with the system DRAM, as accesses generally need to process information from both the DRAM and the directory at the same time (an exception is noted below). The directory and memory banks are interleaved on a cache-line basis, using as many modules as specified with the ``-I'' option. The directory is responsible for maintaining the current state of a cache line, serializing accesses to each line, generating and collecting coherence messages, sending replies, and handling race conditions. In addition, the directory coherence protocol used in RSIM relies on cache-to-cache transfers and uses replacement messages, as depicted in Figure 3.3. Coherence replies are collected at the directory, and in the case of transfers that require coherence actions (other than cache-to-cache transfers), the data is sent to the requestor only after all coherence replies have been collected.
The DirSim function simulates the actions of the directory and includes many stages based on the current type of access being processed and the progress of that access. The following sections describe each of the stages in the directory.