Sarita Adve's Research Group
University of Illinois at Urbana-Champaign


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  • Memory consistency models: Co-developed the memory models for the C++ and Java programming languages, based on our early work on data-race-free models

  • Hardware reliability: co-developed the concept of lifetime reliability aware architectures and dynamic reliability management

  • Power management: Co-designed GRACE, one of the first systems to implement cross-layer energy management

  • Memory level parallelism: Some of the first papers on exploiting instruction-level parallelism (ILP) for memory system performance

  • Evaluation techniques for shared-memory systems with ILP processors: Developed the widely used RSIM architecture simulator

Our group's research focus is in computer architecture, but we take a full system view of the problems we solve and collaborate closely with faculty and students from other areas, including applications, software, and hardware.

The field of computer architecture is currently undergoing several disruptive changes. Moore's law continues to bestow a wealth of transistors, but converting them into usable performance will require exploiting increasingly higher levels of parallelism or many-core computing. Designing parallel hardware and software that achieve power-efficient, reliable, and scalable performance, however, remains a challenge. We are currently working on the following projects to address this challenge:

    SWAT: Software Anomaly Treatment
    DeNovo: Rethinking Hardware for Disciplined Parallelism
    DPJ: Deterministic Parallel Java (led by Vikram Adve)
    Heterogeneous Computing (joint project with Vikram Adve)


Sarita Adve's Group Picture

(front) Abdulrahman Mahmoud, Khalique Ahmed, Sarita Adve, and Matt Sinclair,

(back) Lin Cheng, Gio Salvador, Muhammad Huzaifa, Radha Venkatagiri, John Alsop